Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping. - Yijiang Guo; Jiarui Wang; Jiaxi Zhang 001; Guojie Luo (DAC, 2021)

METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators. - Zhao Wang; Guangyu Sun 003; Jingchen Zhu; Zhe Zhou 002; Yijiang Guo; Zhihang Yuan (CoRR, 2021)

EasyMAC: Design Exploration-Enabled Multiplier-Accumulator Generator Using a Canonical Architectural Representation: (Invited Paper). - Jiaxi Zhang 001; Qiuyang Gao; Yijiang Guo; Bizhao Shi; Guojie Luo (ASP-DAC, 2022)

Purlin: A Versatile Toolkit for the Generation and Simulation of On-Chip Networks. - Yijiang Guo; Xinming Wei; Jiaxi Zhang 001; Guojie Luo (ICCD, 2022)