Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. - Chen Zhang 001; Peng Li 031; Guangyu Sun 003; Yijin Guan; Bingjun Xiao; Jason Cong (FPGA, 2015)

Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators. - Yijin Guan; Ningyi Xu; Chen Zhang 001; Zhihang Yuan; Jason Cong (APPT, 2017)

FPGA-based accelerator for long short-term memory recurrent neural networks. - Yijin Guan; Zhihang Yuan; Guangyu Sun 003; Jason Cong (ASP-DAC, 2017)

FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. - Yijin Guan; Hao Liang 003; Ningyi Xu; Wenqiang Wang; Shaoshuai Shi; Xi Chen 107; Guangyu Sun 003; Wei Zhang 012; Jason Cong (FCCM, 2017)

GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks. - Zhao Wang; Yijin Guan; Guangyu Sun 003; Dimin Niu; Yuhao Wang 002; Hongzhong Zheng; Yinhe Han 001 (ACA, 2020)

Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs. - Yijin Guan; Guangyu Sun 003; Zhihang Yuan; Xingchen Li; Ningyi Xu; Shu Chen; Jason Cong; Yuan Xie 001 (IEEE Trans. Computers, 2020)

BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices. - Zhe Zhou 002; Bizhao Shi; Zhe Zhang 006; Yijin Guan; Guangyu Sun 003; Guojie Luo (DAC, 2021)

Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. - Zhaoyang Du; Yijin Guan; Tianchan Guan; Dimin Niu; Nianxiong Tan; Xiaopeng Yu 002; Hongzhong Zheng; Jianyi Meng; Xiaolang Yan; Yuan Xie 001 (ICPADS, 2022)

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network. - Shuangchen Li; Dimin Niu; Yuhao Wang 002; Wei Han; Zhe Zhang 006; Tianchan Guan; Yijin Guan; Heng Liu; Linyong Huang; Zhaoyang Du; Fei Xue; Yuanwei Fang; et al. (ISCA, 2022)

184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. - Dimin Niu; Shuangchen Li; Yuhao Wang 002; Wei Han; Zhe Zhang 006; Yijin Guan; Tianchan Guan; Fei Sun; Fei Xue; Lide Duan; Yuanwei Fang; Hongzhong Zheng; et al. (ISSCC, 2022)

OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. - Zhaoyang Du; Yijin Guan; Tianchan Guan; Dimin Niu; Linyong Huang; Hongzhong Zheng; Yuan Xie 001 (IEEE Access, 2022)

Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging. - Zhaoyang Du; Yijin Guan; Tianchan Guan; Dimin Niu; Hongzhong Zheng; Yuan Xie 001 (IEEE Access, 2022)

Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network. - Linyong Huang; Zhe Zhang 006; Shuangchen Li; Dimin Niu; Yijin Guan; Hongzhong Zheng; Yuan Xie 001 (IEEE Access, 2022)

Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping. - Xingchen Li; Zhihang Yuan; Yijin Guan; Guangyu Sun 003; Tao Zhang 032; Rongshan Wei; Dimin Niu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators. - Qilin Zheng; Xingchen Li; Yijin Guan; Zongwei Wang 001; Yimao Cai; Yiran Chen 001; Guangyu Sun 003; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Salus: A Practical Trusted Execution Environment for CPU-FPGA Heterogeneous Cloud Platforms. - Yu Zou; Yiran Li; Sheng Wang 011; Le Su; Zhen Gu; Yanheng Lu; Yijin Guan; Dimin Niu; Mingyu Gao 001; Yuan Xie 001; Feifei Li 001 (ASPLOS (4), 2024)

HydraRPC: RPC in the CXL Era. - Teng Ma 006; Zheng Liu; Chengkun Wei; Jialiang Huang; Youwei Zhuo; Haoyu Li; Ning Zhang; Yijin Guan; Dimin Niu; Mingxing Zhang; Tao Ma 006 (USENIX ATC, 2024)

CTXNL: A Software-Hardware Co-designed Solution for Efficient CXL-Based Transaction Processing. - Zhao Wang; Yiqi Chen; Cong Li; Yijin Guan; Dimin Niu; Tianchan Guan; Zhaoyang Du; Xingda Wei; Guangyu Sun 003 (ASPLOS (2), 2025)