A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. - Hao-I Yang; Shih-Chi Yang; Mao-Chih Hsia; Yung-Wei Lin; Yi-Wei Lin; Chien-Hen Chen; Chi-Shin Chang; Geng-Cing Lin; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; et al. (SoCC, 2011)

A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits. - Chia-Hao Pao; Ming-Long Fan; Ming-Fu Tsai; Yin-Nien Chen; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (APCCAS, 2012)

A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance. - Yin-Nien Chen; Ming-Long Fan; Vita Pi-Ho Hu; Ming-Fu Tsai; Chia-Hao Pao; Pin Su; Ching-Te Chuang (ESSDERC, 2012)

Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source. - Chia-Hao Pao; Ming-Long Fan; Ming-Fu Tsai; Yin-Nien Chen; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (ICICDT, 2012)

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. - Hao-I Yang; Yi-Wei Lin; Mao-Chih Hsia; Geng-Cing Lin; Chi-Shin Chang; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Nan-Chun Lien; Hung-Yu Li; Kuen-Di Lee; et al. (ISCAS, 2012)

Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications. - Ming-Long Fan; Vita Pi-Ho Hu; Yin-Nien Chen; Pin Su; Ching-Te Chuang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits. - Shao-Yu Yang; Yin-Nien Chen; Ming-Long Fan; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (ICICDT, 2013)

Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling. - Ming-Long Fan; Vita Pi-Ho Hu; Yin-Nien Chen; Pin Su; Ching-Te Chuang (ISCAS, 2014)

Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell. - Yin-Nien Chen; Ming-Long Fan; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (ISLPED, 2014)

Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits. - Yin-Nien Chen; Ming-Long Fan; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits. - Ming-Long Fan; Shao-Yu Yang; Vita Pi-Ho Hu; Yin-Nien Chen; Pin Su; Ching-Te Chuang (Microelectron. Reliab., 2014)

Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices. - Yin-Nien Chen; Ming-Long Fan; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices. - Tse-Ching Wu; Chien-Ju Chen; Yin-Nien Chen; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (ICICDT, 2015)

Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. - Chien-Ju Chen; Yin-Nien Chen; Ming-Long Fan; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (ISCAS, 2015)

Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. - Tse-Ching Wu; Chien-Ju Chen; Yin-Nien Chen; Vita Pi-Ho Hu; Pin Su; Ching-Te Chuang (SoCC, 2015)

Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling. - Jian-Hao Wang; Yin-Nien Chen; Pin Su; Ching-Te Chuang (ICICDT, 2016)

Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. - Chia-Ning Chang; Yin-Nien Chen; Po-Tsang Huang; Pin Su; Ching-Te Chuang (ISCAS, 2017)