A low-voltage input buffer with linearity-enhancement scheme for a 500MS/s Pipelined-SAR ADC achieving SFDR > 79dBc. - Fangyuan Xu; Yina Shangguan; Xuan Guo 003; Hanbo Jia; Yun Bai; Kai Sun; Xinyu Liu 004 (Microelectron. J., 2026)