A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs. - Didem Turker; Ade Bekele; Parag Upadhyaya; Bob Verbruggen; Ying Cao 010; Shaojun Ma; Christophe Erdmann; Brendan Farley; Yohan Frans; Ken Chang (ISSCC, 2018)

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. - Jay Im; Kevin Zheng; Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (ISSCC, 2020)

A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET. - Chi Fung Poon; Wenfeng Zhang; Junho Cho; Shaojun Ma; Yipeng Wang 003; Ying Cao 010; Asma Laraba; Eugene Ho; Winson Lin; Zhaoyin Daniel Wu; Kee Hian Tan; Parag Upadhyaya; et al. (VLSI Circuits, 2021)

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. - Jay Im; Kevin Zheng; Chuen-Huei Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (IEEE J. Solid State Circuits, 2021)

A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET. - Chi Fung Poon; Wenfeng Zhang; Junho Cho; Shaojun Ma; Yipeng Wang 003; Ying Cao 010; Asma Laraba; Eugene Ho; Winson Lin; Zhaoyin Daniel Wu; Kee Hian Tan; Parag Upadhyaya; et al. (IEEE J. Solid State Circuits, 2022)

A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies. - Mayank Raj; Chuan Xie; Ade Bekele; Adam Chou; Wenfeng Zhang; Ying Cao 010; Jae Wook Kim; Nakul Narang; Hongyuan Zhao; Yipeng Wang 003; Kee Hian Tan; Winson Lin; et al. (ISSCC, 2023)