A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE. - Shiva Kiran; Shengchang Cai; Ying Luo 010; Sebastian Hoyos; Samuel Palermo (CICC, 2019)

A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS. - Shiva Kiran; Shengchang Cai; Ying Luo 010; Sebastian Hoyos; Samuel Palermo (IEEE J. Solid State Circuits, 2019)