ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. - Jinn-Shyan Wang; Yung-Chen Chien; Jia-Hong Lin; Chun-Yuan Cheng; Ying-Ting Ma; Chung-Hsun Huang (ASICON, 2011)

Design of a Low-Voltage Low-Dropout Regulator. - Chung-Hsun Huang; Ying-Ting Ma; Wei-Chen Liao (IEEE Trans. Very Large Scale Integr. Syst., 2014)