Efficient Filtering Query Indexing in Data Stream. - Ying Wang 001; Shuo Bai; Jianlong Tan; Li Guo 001 (WISE Workshops, 2006)

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (PRDC, 2010)

Wear rate leveling: lifetime enhancement of PRAM with endurance variation. - Jianbo Dong; Lei Zhang 008; Yinhe Han 001; Ying Wang 001; Xiaowei Li 001 (DAC, 2011)

Flex memory: Exploiting and managing abundant off-chip optical bandwidth. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2011)

Scheduling Mixed Real-Time and Non-real-Time Applications in MapReduce Environment. - Xicheng Dong; Ying Wang 001; Huaming Liao (ICPADS, 2011)

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction. - Yinhe Han 001; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ISCAS, 2013)

A low power DRAM refresh control scheme for 3D memory cube. - Ying Wang 001; Yinhe Han 001; Huawei Li 001 (COOL Chips, 2014)

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube. - Yinhe Han 001; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2014)

Reinventing Memory System Design for Many-Accelerator Architecture. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001 (J. Comput. Sci. Technol., 2014)

ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation. - Hang Lu; Guihai Yan; Yinhe Han 001; Ying Wang 001; Xiaowei Li 001 (ASP-DAC, 2015)

A Lightweight Timing Channel Protection for Shared Memory Controllers. - Guopei Liu; Ying Wang 001; Sen Li; Huawei Li 001; Xiaowei Li 001 (ATS, 2015)

TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs. - Jun Zhou 022; Huawei Li 001; Tiancheng Wang; Sen Li; Ying Wang 001; Xiaowei Li 001 (ATS, 2015)

TURO: A lightweight turn-guided routing scheme for 3D NoCs. - Jun Zhou 022; Huawei Li 001; Tiancheng Wang; Ying Wang 001; Xiaowei Li 001 (COOL Chips, 2015)

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. - Ying Wang 001; Yinhe Han 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2015)

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory. - Ying Wang 001; Yinhe Han 001; Cheng Wang; Huawei Li 001; Xiaowei Li 001 (DAC, 2015)

Retraining-based timing error mitigation for hardware neural networks. - Jiachao Deng; Yuntan Fang; Zidong Du; Ying Wang 001; Huawei Li 001; Olivier Temam; Paolo Ienne; David Novo; Xiaowei Li 001; Yunji Chen; Chengyong Wu (DATE, 2015)

A case of precision-tunable STT-RAM memory design for approximate neural network. - Ying Wang 001; Lili Song; Yinhe Han 001; Yuanqing Cheng; Huawei Li 001; Xiaowei Li 001 (ISCAS, 2015)

A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans. - Yun Cheng; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ISVLSI, 2015)

An architecture-level cache simulation framework supporting advanced PMA STT-MRAM. - Bi Wu; Yuanqing Cheng; Ying Wang 001; Aida Todri-Sanial; Guangyu Sun 003; Lionel Torres; Weisheng Zhao (NANOARCH, 2015)

A signal degradation reduction method for memristor ratioed logic (MRL) gates. - Bosheng Liu; Ying Wang 001; Zhiqiang You; Yinhe Han 001; Xiaowei Li 001 (IEICE Electron. Express, 2015)

RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors. - Hang Lu; Binzhang Fu; Ying Wang 001; Yinhe Han 001; Guihai Yan; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Economizing TSV Resources in 3-D Network-on-Chip Design. - Ying Wang 001; Yinhe Han 001; Lei Zhang 008; Binzhang Fu; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Data Remapping for Static NUCA in Degradable Chip Multiprocessors. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization. - Lili Song; Ying Wang 001; Yinhe Han 001; Xin Zhao 044; Bosheng Liu; Xiaowei Li 001 (DAC, 2016)

DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. - Ying Wang 001; Yinhe Han 001; Jun Zhou 022; Huawei Li 001; Xiaowei Li 001 (DAC, 2016)

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. - Ying Wang 001; Jie Xu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2016)

Frequency scheduling for resilient chip multi-processors operating at Near Threshold Voltage. - Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2016)

Re-architecting the on-chip memory sub-system of machine-learning accelerator for embedded devices. - Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2016)

Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation. - Yinhe Han 001; Jianbo Dong; Kaiheng Weng; Ying Wang 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. - Ying Wang 001; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. - Ying Wang 001; Yinhe Han 001; Huawei Li 001; Lei Zhang 008; Yuanqing Cheng; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems. - Shiqi Lian; Ying Wang 001; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2017)

ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory. - Yibin Tang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2017)

CNN-based object detection solutions for embedded heterogeneous multicore SoCs. - Cheng Wang; Ying Wang 001; Yinhe Han 001; Lili Song; Zhenyu Quan; Jiajun Li; Xiaowei Li 001 (ASP-DAC, 2017)

Test and Reliability of Emerging Non-volatile Memories. - Said Hamdioui; Peyman Pouyan; Huawei Li 001; Ying Wang 001; Arijit Raychowdhury; Insik Yoon (ATS, 2017)

Selective off-loading to Memory: Task Partitioning and Mapping for PIM-enabled Heterogeneous Systems. - Dawen Xu 002; Yi Liao; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (Conf. Computing Frontiers, 2017)

Dadu: Accelerating Inverse Kinematics for High-DOF Robots. - Shiqi Lian; Yinhe Han 001; Ying Wang 001; Yungang Bao; Hang Xiao; Xiaowei Li 001; Ninghui Sun (DAC, 2017)

Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR. - Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2017)

Cross-program design space exploration by ensemble transfer learning. - Dandan Li; Shuzhen Yao; Senzhang Wang; Ying Wang 001 (ICCAD, 2017)

Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. - Bi Wu; Yuanqing Cheng; Pengcheng Dai; Jianlei Yang 001; Youguang Zhang; Dijun Liu; Ying Wang 001; Weisheng Zhao (ICCAD, 2017)

A Coflow-Based Co-Optimization Framework for High-Performance Data Analytics. - Long Cheng 003; Ying Wang 001; Yulong Pei; Dick H. J. Epema (ICPP, 2017)

Flip-flop clustering based trace signal selection for post-silicon debug. - Yun Cheng; Huawei Li 001; Ying Wang 001; Yingke Gao; Bo Liu 018; Xiaowei Li 001 (VTS, 2017)

Power-Utility-Driven Write Management for MLC PCM. - Bing Li 017; Yu Hu 001; Ying Wang 001; Jing Ye 001; Xiaowei Li 001 (ACM J. Emerg. Technol. Comput. Syst., 2017)

Retention-Aware DRAM Assembly and Repair for Future FGR Memories. - Ying Wang 001; Yinhe Han 001; Cheng Wang; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. - Lili Song; Ying Wang 001; Yinhe Han 001; Huawei Li 001; Yuanqing Cheng; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips. - Ying Wang 001; Jiachao Deng; Yuntan Fang; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

PIMCH: Cooperative memory prefetching in processing-in-memory architecture. - Sheng Xu; Ying Wang 001; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2018)

XORiM: A case of in-memory bit-comparator implementation and its performance implications. - Kaiwei Zou; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2018)

Dadu-P: a scalable accelerator for robot motion planning in a dynamic environment. - Shiqi Lian; Yinhe Han 001; Xiaoming Chen 003; Ying Wang 001; Hang Xiao (DAC, 2018)

A retrospective evaluation of energy-efficient object detection solutions on embedded devices. - Ying Wang 001; Zhenyu Quan; Jiajun Li; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2018)

Caching or Not: Rethinking Virtual File System for Non-Volatile Main Memory. - Ying Wang 001; Dejun Jiang 001; Jin Xiong (HotStorage, 2018)

FCN-engine: accelerating deconvolutional layers in classic CNN processors. - Dawen Xu 002; Kaijie Tu; Ying Wang 001; Cheng Liu 008; Bingsheng He; Huawei Li 001 (ICCAD, 2018)

NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs. - Chen Liu; Yuanqing Cheng; Ying Wang 001; Youguang Zhang; Weisheng Zhao (ISCAS, 2018)

MTTF-Aware Reliability Task Scheduling for PIM-Based Heterogeneous Computing System. - Desong Pang; Dawen Xu 002; Ying Wang 001; Huaguo Liang (ITC-Asia, 2018)

Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-processors. - Ying Wang 001; Wen Li; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2018)

Lightweight Timing Channel Protection for Shared DRAM Controller. - Ying Wang 001; Wen Li; Huawei Li 001; Xiaowei Li 001 (ITC, 2018)

Exploiting Lightweight Statistical Learning for Event-Based Vision Processing. - Cong Shi 003; Jiajun Li; Ying Wang 001; Gang Luo 003 (IEEE Access, 2018)

Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach. - Xiaowei Li 001; Guihai Yan; Jing Ye 001; Ying Wang 001 (Sci. China Inf. Sci., 2018)

DimRouter: A Multi-Mode Router Architecture for Higher Energy-Proportionality of On-Chip Networks. - Shiqi Lian; Ying Wang 001; Yinhe Han 001 (J. Comput. Sci. Technol., 2018)

On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug. - Yun Cheng; Huawei Li 001; Ying Wang 001; Haihua Shen; Bo Liu 018; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors. - Ying Wang 001; Huawei Li 001; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators. - Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Resilient Neural Network Training for Accelerators with Computing Errors. - Dawen Xu 002; KouZi Xing; Cheng Liu 008; Ying Wang 001; Yulin Dai; Long Cheng 003; Huawei Li 001; Lei Zhang 008 (ASAP, 2019)

Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators. - Jiajun Li; Ying Wang 001; Bosheng Liu; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2019)

P3M: a PIM-based neural network model protection scheme for deep learning accelerator. - Wen Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2019)

Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators. - Bosheng Liu; Xiaoming Chen 003; Ying Wang 001; Yinhe Han 001; Jiajun Li; Haobo Xu; Xiaowei Li 001 (ASP-DAC, 2019)

CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems. - Sheng Xu; Xiaoming Chen 003; Ying Wang 001; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2019)

Exploring emerging CNFET for efficient last level cache design. - Dawen Xu 002; Li Li; Ying Wang 001; Cheng Liu 008; Huawei Li 001 (ASP-DAC, 2019)

A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs. - Ying Wang 001; Shengwen Liang; Huawei Li 001; Xiaowei Li 001 (DAC, 2019)

Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Cong Shi 003; Xiaowei Li 001 (DAC, 2019)

Learn-to-Scale: Parallelizing Deep Learning Inference on Chip Multiprocessor Architecture. - Kaiwei Zou; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2019)

InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing. - Shengwen Liang; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (FPL, 2019)

An Agile Precision-Tunable CNN Accelerator based on ReRAM. - Yintao He; Ying Wang 001; Yongchen Wang; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2019)

ACG-Engine: An Inference Accelerator for Content Generative Neural Networks. - Haobo Xu; Ying Wang 001; Yujie Wang; Jiajun Li; Bosheng Liu; Yinhe Han 001 (ICCAD, 2019)

RRAMedy: Protecting ReRAM-Based Neural Network from Permanent and Soft Faults During Its Lifetime. - Wen Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCD, 2019)

OBFS: OpenCL Based BFS Optimizations on Software Programmable FPGAs. - Cheng Liu 008; Xinyu Chen 001; Bingsheng He; Xiaofei Liao; Ying Wang 001; Lei Zhang 008 (FPT, 2019)

Squeezing the Last MHz for CNN Acceleration on FPGAs. - Li Li; Dawen Xu 002; Kouzi Xing; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2019)

Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval. - Shengwen Liang; Ying Wang 001; Youyou Lu; Zhe Yang 012; Huawei Li 001; Xiaowei Li 001 (USENIX ATC, 2019)

Leveraging Memory PUFs and PIM-based encryption to secure edge deep learning systems. - Wen Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (VTS, 2019)

Modeling of Mixing Uniformity for Food With Special Medicinal Purposes Based on Chinese Herbal Medicine. - Ke Han; Lei Zhang 008; Ying Wang 001; Miao Wang; Mian Guo; Huan Li; Yu Zhang 027; Ming Zhao; Qian Zhao; Chunyu Wang; Rui Zhang 040 (IEEE Access, 2019)

PIMSim: A Flexible and Detailed Processing-in-Memory Simulator. - Sheng Xu; Xiaoming Chen 003; Ying Wang 001; Yinhe Han 001; Xuehai Qian; Xiaowei Li 001 (IEEE Comput. Archit. Lett., 2019)

Correlation of Gut Microbiome Between ASD Children and Mothers and Potential Biomarkers for Risk Assessment. - Ning Li; Junjie Yang; Jiaming Zhang; Cheng Liang 001; Ying Wang 001; Bin Chen; Changying Zhao; Jingwen Wang; Guangye Zhang; Dongmei Zhao; Yi Liu; Lehai Zhang; et al. (Genom. Proteom. Bioinform., 2019)

Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator. - Shichang Zhang; Ying Wang 001; Xiaoming Chen 003; Yinhe Han 001; Yujie Wang; Xiaowei Li 001 (IEICE Electron. Express, 2019)

MV-Net: Toward Real-Time Deep Learning on Mobile GPGPU Systems. - Yibin Tang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ACM J. Emerg. Technol. Comput. Syst., 2019)

Load-balancing distributed outer joins through operator decomposition. - Long Cheng 003; Spyros Kotoulas; Qingzhi Liu; Ying Wang 001 (J. Parallel Distributed Comput., 2019)

A QoS-QoR Aware CNN Accelerator Design Approach. - Ying Wang 001; Huawei Li 001; Long Cheng 003; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug. - Yun Cheng; Huawei Li 001; Ying Wang 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design. - Bi Wu; Beibei Zhang; Yuanqing Cheng; Ying Wang 001; Dijun Liu; Weisheng Zhao (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System. - Dawen Xu 002; Ziyang Zhu; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Lei Zhang 008; Kwang-Ting Cheng (ASAP, 2020)

Search-free Accelerator for Sparse Convolutional Neural Networks. - Bosheng Liu; Xiaoming Chen 003; Yinhe Han 001; Ying Wang 001; Jiajun Li; Haobo Xu; Xiaowei Li 001 (ASP-DAC, 2020)

Towards State-Aware Computation in ReRAM Neural Networks. - Yintao He; Ying Wang 001; Xiandong Zhao; Huawei Li 001; Xiaowei Li 001 (DAC, 2020)

RaQu: An automatic high-utilization CNN quantization and mapping framework for general-purpose RRAM Accelerator. - Songyun Qu; Bing Li 017; Ying Wang 001; Dawen Xu 002; Xiandong Zhao; Lei Zhang 008 (DAC, 2020)

An Efficient Deep Learning Accelerator for Compressed Video Analysis. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Yinhe Han 001; Xiaowei Li 001 (DAC, 2020)

BitPruner: Network Pruning for Bit-serial Accelerators. - Xiandong Zhao; Ying Wang 001; Cheng Liu 008; Cong Shi 003; Kaijie Tu; Lei Zhang 008 (DAC, 2020)

CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding. - Dawen Xu 002; Kexin Chu; Cheng Liu 008; Ying Wang 001; Lei Zhang 008; Huawei Li 001 (DATE, 2020)

You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design. - Weiwei Chen; Ying Wang 001; Shuang Yang; Chen Liu; Lei Zhang 008 (DATE, 2020)

Towards Best-effort Approximation: Applying NAS to General-purpose Approximate Computing. - Weiwei Chen; Ying Wang 001; Shuang Yang; Chen Liu; Lei Zhang 008 (DATE, 2020)

Multi-task Scheduling for PIM-based Heterogeneous Computing System. - Dawen Xu 002; Cheng Chu; Cheng Liu 008; Ying Wang 001; Xianzhong Zhou; Lei Zhang 008; Huaguo Liang; Huawei Li 001 (ACM Great Lakes Symposium on VLSI, 2020)

HitM: High-Throughput ReRAM-based PIM for Multi-Modal Neural Networks. - Bing Li 017; Ying Wang 001; Yiran Chen 001 (ICCAD, 2020)

DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. - Shengwen Liang; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2020)

A Many-Core Accelerator Design for On-Chip Deep Reinforcement Learning. - Ying Wang 001; Mengdi Wang; Bing Li 017; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2020)

A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators. - Dawen Xu 002; Cheng Chu; Qianlong Wang; Cheng Liu 008; Ying Wang 001; Lei Zhang 008; Huaguo Liang; Kwang-Ting Cheng (ICCD, 2020)

Linear Symmetric Quantization of Neural Networks for Low-precision Integer Hardware. - Xiandong Zhao; Ying Wang 001; Xuyi Cai; Cheng Liu 008; Lei Zhang 008 (ICLR, 2020)

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis. - Rajendra Bishnoi; Lizhou Wu; Moritz Fieback; Christopher Münch; Sarath Mohanachandran Nair; Mehdi Baradaran Tahoori; Ying Wang 001; Huawei Li 001; Said Hamdioui (VTS, 2020)

Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization. - Jiacheng Ni; Keren Liu; Bi Wu; Weisheng Zhao; Yuanqing Cheng; Xiaolong Zhang; Ying Wang 001 (ACM J. Emerg. Technol. Comput. Syst., 2020)

A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification. - Wei He; Jinguo Huang; Tengxiao Wang; Yingcheng Lin; Junxian He; Xichuan Zhou; Ping Li 042; Ying Wang 001; Nanjian Wu; Cong Shi 003 (Sensors, 2020)

Accelerating Generative Neural Networks on Unmodified Deep Learning Processors - A Software Approach. - Dawen Xu 002; Cheng Liu 008; Ying Wang 001; Kaijie Tu; Bingsheng He; Lei Zhang 008 (IEEE Trans. Computers, 2020)

A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration. - Bi Wu; Pengcheng Dai; Yuanqing Cheng; Ying Wang 001; Jianlei Yang 001; Zhaohao Wang; Dijun Liu; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Field-Free 3T2SOT MRAM for Non-Volatile Cache Memories. - Bi Wu; Chao Wang 094; Zhaohao Wang; Ying Wang 001; Deming Zhang; Dijun Liu; Youguang Zhang; Xiaobo Sharon Hu (IEEE Trans. Circuits Syst., 2020)

Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. - Bi Wu; Weisheng Zhao; Xiaobo Sharon Hu; Pengcheng Dai; Zhaohao Wang; Chao Wang 094; Ying Wang 001; Jianlei Yang 001; Yuanqing Cheng; Dijun Liu; Youguang Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Exploiting Memristors for Neuromorphic Reinforcement Learning. - Cong Shi 003; Jing Lu; Ying Wang 001; Ping Li 042; Min Tian (AICAS, 2021)

VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack. - Hao Lv; Bing Li 017; Ying Wang 001; Cheng Liu 008; Lei Zhang 008 (ASP-DAC, 2021)

An Intelligent Video Processing Architecture for Edge-cloud Video Streaming. - Chengsi Gao; Ying Wang 001; Weiwei Chen; Lei Zhang 008 (DAC, 2021)

GCiM: A Near-Data Processing Accelerator for Graph Construction. - Lei He 016; Cheng Liu 008; Ying Wang 001; Shengwen Liang; Huawei Li 001; Xiaowei Li 001 (DAC, 2021)

TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning. - Yintao He; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2021)

ASBP: Automatic Structured Bit-Pruning for RRAM-based NN Accelerator. - Songyun Qu; Bing Li 017; Ying Wang 001; Lei Zhang 008 (DAC, 2021)

PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2021)

Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization. - Mengdi Wang; Ying Wang 001; Cheng Liu 008; Lei Zhang 008 (DAC, 2021)

RECOIN: A Low-Power Processing-in-ReRAM Architecture for Deformable Convolution. - Cheng Chu; Fan Chen 001; Dawen Xu 002; Ying Wang 001 (ACM Great Lakes Symposium on VLSI, 2021)

Tenet: A Neural Network Model Extraction Attack in Multi-core Architecture. - Chengsi Gao; Bing Li 017; Ying Wang 001; Weiwei Chen; Lei Zhang 008 (ACM Great Lakes Symposium on VLSI, 2021)

MT-DLA: An Efficient Multi-Task Deep Learning Accelerator Design. - Mengdi Wang; Bing Li 017; Ying Wang 001; Cheng Liu 008; Xiaohan Ma; Xiandong Zhao; Lei Zhang 008 (ACM Great Lakes Symposium on VLSI, 2021)

PicoVO: A Lightweight RGB-D Visual Odometry Targeting Resource-Constrained IoT Devices. - Yuquan He; Ying Wang 001; Cheng Liu 008; Lei Zhang 008 (ICRA, 2021)

NASA: Accelerating Neural Network Design with a NAS Processor. - Xiaohan Ma; Chang Si; Ying Wang 001; Cheng Liu 008; Lei Zhang 008 (ISCA, 2021)

Optimus: towards optimal layer-fusion on deep learning processors. - Xuyi Cai; Ying Wang 001; Lei Zhang 008 (LCTES, 2021)

CHaNAS: coordinated search for network architecture and scheduling policy. - Weiwei Chen; Ying Wang 001; Gangliang Lin; Chengsi Gao; Cheng Liu 008; Lei Zhang 008 (LCTES, 2021)

GLIST: Towards In-Storage Graph Learning. - Cangyuan Li; Ying Wang 001; Cheng Liu 008; Shengwen Liang; Huawei Li 001; Xiaowei Li 001 (USENIX ATC, 2021)

Special Session - Test for AI Chips: from DFT to On-line Testing. - Huawei Li 001; Xiaowei Li 001; Yu Huang 005; Ying Wang 001; Gary Guo (VTS, 2021)

To cloud or not to cloud: an on-line scheduler for dynamic privacy-protection of deep learning workload on edge devices. - Yibin Tang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CCF Trans. High Perform. Comput., 2021)

Energy-Efficient Accelerator Design for Deformable Convolution Networks. - Dawen Xu 002; Cheng Chu; Cheng Liu 008; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Kwang-Ting Cheng (CoRR, 2021)

Taming Process Variations in CNFET for Efficient Last Level Cache Design. - Dawen Xu 002; Zhuangyu Feng; Cheng Liu 008; Li Li; Ying Wang 001; Yuanqing Cheng; Huawei Li 001; Xiaowei Li 001 (CoRR, 2021)

Enhancing the security of memory in cloud infrastructure through in-phase change memory data randomisation. - Xianzhong Zhou; Ying Wang 001 (IET Comput. Digit. Tech., 2021)

CompSNN: A lightweight spiking neural network based on spatiotemporally compressive spike features. - Tengxiao Wang; Cong Shi 003; Xichuan Zhou; Yingcheng Lin; Junxian He; Ping Gan; Ping Li 042; Ying Wang 001; Liyuan Liu; Nanjian Wu; Gang Luo 003 (Neurocomputing, 2021)

EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks. - Shengwen Liang; Ying Wang 001; Cheng Liu 008; Lei He 016; Huawei Li 001; Dawen Xu 002; Xiaowei Li 001 (IEEE Trans. Computers, 2021)

An Edge 3D CNN Accelerator for Low-Power Activity Recognition. - Ying Wang 001; Yongchen Wang; Cong Shi 003; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Dadu-Eye: A 5.3 TOPS/W, 30 fps/1080p High Accuracy Stereo Vision Accelerator. - Feng Min; Haobo Xu; Ying Wang 001; Yujie Wang; Jiajun Li; Xingqi Zou; Bei Li; Yinhe Han 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A NAND-SPIN-Based Magnetic ADC. - Bi Wu; Zhaohao Wang; Yuxuan Li; Ying Wang 001; Dijun Liu; Weisheng Zhao; Xiaobo Sharon Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Network-Aware Locality Scheduling for Distributed Data Operators in Data Centers. - Long Cheng 003; Ying Wang 001; Qingzhi Liu; Dick H. J. Epema; Cheng Liu 008; Ying Mao 001; John Murphy 001 (IEEE Trans. Parallel Distributed Syst., 2021)

R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors. - Dawen Xu 002; Meng He 012; Cheng Liu 008; Ying Wang 001; Long Cheng 003; Huawei Li 001; Xiaowei Li 001; Kwang-Ting Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System. - Dawen Xu 002; Ziyang Zhu; Cheng Liu 008; Ying Wang 001; Shuang Zhao; Lei Zhang 008; Huaguo Liang; Huawei Li 001; Kwang-Ting Cheng (IEEE Trans. Very Large Scale Integr. Syst., 2021)

InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs. - Yintao He; Songyun Qu; Ying Wang 001; Bing Li 017; Huawei Li 001; Xiaowei Li 001 (DAC, 2022)

Processing-in-SRAM acceleration for ultra-low power visual 3D perception. - Yuquan He; Songyun Qu; Gangliang Lin; Cheng Liu 008; Lei Zhang 008; Ying Wang 001 (DAC, 2022)

VStore: in-storage graph based vector search accelerator. - Shengwen Liang; Ying Wang 001; Ziming Yuan; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2022)

Winograd convolution: a perspective from fault tolerance. - Xinghua Xue; Haitong Huang; Cheng Liu 008; Tao Luo 014; Lei Zhang 008; Ying Wang 001 (DAC, 2022)

NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network. - Fuping Li; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (DATE, 2022)

MOCCA: A Process Variation Tolerant Systolic DNN Accelerator using CNFETs in Monolithic 3D. - Samuel J. Engers; Cheng Chu; Dawen Xu 002; Ying Wang 001; Fan Chen 001 (ACM Great Lakes Symposium on VLSI, 2022)

GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. - Fuping Li; Ying Wang 001; Yuanqing Cheng; Yujie Wang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2022)

Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance. - Lei Dai; Ying Wang 001; Cheng Liu 008; Fuping Li; Huawei Li 001; Xiaowei Li 001 (ICCD, 2022)

Security Threat to the Robustness of RRAM-based Neuromorphic Computing System. - Bing Li 017; Hao Lv; Ying Wang 001; Yiran Chen 001 (iSES, 2022)

Canopy: A CNFET-based Process Variation Aware Systolic DNN Accelerator. - Cheng Chu; Dawen Xu 002; Ying Wang 001; Fan Chen 001 (ISLPED, 2022)

DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture. - Xuyi Cai; Ying Wang 001; Xiaohan Ma; Yinhe Han 001; Lei Zhang 008 (MICRO, 2022)

LINAC: A Spatially Linear Accelerator for Convolutional Neural Networks. - Hang Xiao; Haobo Xu; Ying Wang 001; Yujie Wang; Yinhe Han 001 (IEEE Comput. Archit. Lett., 2022)

Cognitive SSD+: a deep learning engine for energy-efficient unstructured data retrieval. - Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CCF Trans. High Perform. Comput., 2022)

Survey on chiplets: interface, interconnect and integration methodology. - Xiaohan Ma; Ying Wang 001; Yujie Wang; Xuyi Cai; Yinhe Han 001 (CCF Trans. High Perform. Comput., 2022)

Real-Time Robust Video Object Detection System Against Physical-World Adversarial Attacks. - Husheng Han; Xing Hu 001; Kaidi Xu; Pucheng Dang; Ying Wang 001; Yongwei Zhao; Zidong Du; Qi Guo 001; Yanzhi Yang; Tianshi Chen 002 (CoRR, 2022)

Dadu-SV: Accelerate Stereo Vision Processing on NPU. - Feng Min; Ying Wang 001; Haobo Xu; Junpei Huang; Yujie Wang; Xingqi Zou; Meixuan Lu; Yinhe Han 001 (IEEE Embed. Syst. Lett., 2022)

TripleBrain: A Compact Neuromorphic Hardware Core With Fast On-Chip Self-Organizing and Reinforcement Spike-Timing Dependent Plasticity. - Haibing Wang; Zhen He; Tengxiao Wang; Junxian He; Xichuan Zhou; Ying Wang 001; Liyuan Liu; Nanjian Wu; Min Tian; Cong Shi 003 (IEEE Trans. Biomed. Circuits Syst., 2022)

Olympus: Reaching Memory-Optimality on DNN Processors. - Xuyi Cai; Ying Wang 001; Kaijie Tu; Chengsi Gao; Lei Zhang 008 (IEEE Trans. Computers, 2022)

CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures. - Kaiwei Zou; Ying Wang 001; Long Cheng 003; Songyun Qu; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Computers, 2022)

Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial Learning. - Weiwei Chen; Ying Wang 001; Ying Xu; Chengsi Gao; Yinhe Han 001; Lei Zhang 008 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing. - Yintao He; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Automated Quantization Framework for High-Utilization RRAM-Based PIM. - Bing Li 017; Songyun Qu; Ying Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning. - Cheng Liu 008; Cheng Chu; Dawen Xu 002; Ying Wang 001; Qianlong Wang; Huawei Li 001; Xiaowei Li 001; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Fast Precision Tuning Solution for Always-On DNN Accelerators. - Ying Wang 001; Yintao He; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning. - Zhen He; Cong Shi 003; Tengxiao Wang; Ying Wang 001; Min Tian; Xichuan Zhou; Ping Li 042; Liyuan Liu; Nanjian Wu; Gang Luo 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

MPC-CSAS: Multi-Party Computation for Real-Time Privacy-Preserving Speed Advisory Systems. - Mingming Liu 001; Long Cheng 003; Yingqi Gu; Ying Wang 001; Qingzhi Liu; Noel E. O'Connor (IEEE Trans. Intell. Transp. Syst., 2022)

Taming Process Variations in CNFET for Efficient Last-Level Cache Design. - Dawen Xu 002; Zhuangyu Feng; Cheng Liu 008; Li Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Deep Learning Compiler Optimization on Multi-Chiplet Architecture. - Huiqing Xu; Kuang Mao; Quihong Pan; Zhaorong Tang; Mengdi Wang; Ying Wang 001 (AICAS, 2023)

Occamy: Elastically Sharing a SIMD Co-processor across Multiple CPU Cores. - Zhongcheng Zhang; Yan Ou; Ying Liu 055; Chenxi Wang; Yongbin Zhou; Xiaoyu Wang; Yuyang Zhang; Yucheng Ouyang; Jiahao Shan; Ying Wang 001; Jingling Xue; Huimin Cui; et al. (ASPLOS (3), 2023)

Adversarial Testing: A Novel On-Line Testing Method for Deep Learning Processors. - Wen Li; Ying Wang 001; Kaiwei Zou; Huawei Li 001; Xiaowei Li 001 (ATS, 2023)

AmgR: Algebraic Multigrid Accelerated on ReRAM. - Mingjia Fan; Xiaotian Tian; Yintao He; Junxian Li; Yiru Duan; Xiaozhe Hu; Ying Wang 001; Zhou Jin 001; Weifeng Liu 002 (DAC, 2023)

APPEND: Rethinking ASIP Synthesis in the Era of AI. - Cangyuan Li; Ying Wang 001; Huawei Li 001; Yinhe Han 001 (DAC, 2023)

Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity. - Chengsi Gao; Ying Wang 001; Cheng Liu 008; Mengdi Wang; Weiwei Chen; Yinhe Han 001; Lei Zhang 008 (DATE, 2023)

ENASA: Towards Edge Neural Architecture Search based on CIM acceleration. - Shixin Zhao; Songyun Qu; Ying Wang 001; Yinhe Han 001 (DATE, 2023)

CTA: Hardware-Software Co-design for Compressed Token Attention Mechanism. - Haoran Wang 012; Haobo Xu; Ying Wang 001; Yinhe Han 001 (HPCA, 2023)

Efficient Supernet Training Using Path Parallelism. - Ying Xu; Long Cheng 003; Xuyi Cai; Xiaohan Ma; Weiwei Chen; Lei Zhang 008; Ying Wang 001 (HPCA, 2023)

DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. - Erjing Luo; Haitong Huang; Cheng Liu 008; Guoyu Li; Bing Yang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2023)

Full State Quantum Circuit Simulation Beyond Memory Limit. - Yilun Zhao 002; Yu Chen; He Li; Ying Wang 001; Kaiyan Chang; Bingmeng Wang; Bing Li 017; Yinhe Han 001 (ICCAD, 2023)

PANG: A Pattern-Aware GCN Accelerator for Universal Graphs. - Yibo Du; Ying Wang 001; Shengwen Liang; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (ICCD, 2023)

Communication-aware Quantization for Deep Learning Inference Parallelization on Chiplet-based Accelerators. - Kaiwei Zou; Songyun Qu; Wen Li; Ying Wang 001; Huawei Li 001; Yongpan Liu (ICPADS, 2023)

Reliability Analysis of Vision Transformers. - Xinghua Xue; Cheng Liu 008; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

ApproxABFT: Approximate Algorithm-Based Fault Tolerance for Vision Transformers. - Xinghua Xue; Cheng Liu 008; Haitong Huang; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

ChipGPT: How far are we from natural language hardware design. - Kaiyan Chang; Ying Wang 001; Haimeng Ren; Mengdi Wang; Shengwen Liang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing. - Haitong Huang; Cheng Liu 008; Xinghua Xue; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

Cross-Layer Optimization for Fault-Tolerant Deep Learning. - Qing Zhang; Cheng Liu 008; Bo Liu 018; Haitong Huang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

IVP: An Intelligent Video Processing Architecture for Video Streaming. - Chengsi Gao; Ying Wang 001; Yinhe Han 001; Weiwei Chen; Lei Zhang 008 (IEEE Trans. Computers, 2023)

Optimus: An Operator Fusion Framework for Deep Neural Networks. - Xuyi Cai; Ying Wang 001; Lei Zhang 008 (ACM Trans. Embed. Comput. Syst., 2023)

A Framework for Neural Network Architecture and Compile Co-optimization. - Weiwei Chen; Ying Wang 001; Ying Xu; Chengsi Gao; Cheng Liu 008; Lei Zhang 008 (ACM Trans. Embed. Comput. Syst., 2023)

An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs. - Bi Wu; Haonan Zhu; Dayane Reis; Zhaohao Wang; Ying Wang 001; Ke Chen 018; Weiqiang Liu 001; Fabrizio Lombardi; Xiaobo Sharon Hu (IEEE Trans. Emerg. Top. Comput., 2023)

On-Line Fault Protection for ReRAM-Based Neural Networks. - Wen Li; Ying Wang 001; Cheng Liu 008; Yintao He; Lian Liu; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Computers, 2023)

S$^{2}$ Loop: A Lightweight Spectral-Spatio Loop Closure Detector for Resource-Constrained Platforms. - Yuquan He; Long Zhang; Cheng Liu 008; Lei Zhang 008; Ying Wang 001 (IEEE Robotics Autom. Lett., 2023)

A Survey of Non-Volatile Main Memory File Systems. - Ying Wang 001; Wenqing Jia; Dejun Jiang 001; Jin Xiong (J. Comput. Sci. Technol., 2023)

Variation Enhanced Attacks Against RRAM-Based Neuromorphic Computing System. - Hao Lv; Bing Li 017; Lei Zhang 008; Cheng Liu 008; Ying Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Network Pruning for Bit-Serial Accelerators. - Xiandong Zhao; Ying Wang 001; Cheng Liu 008; Cong Shi 003; Kaijie Tu; Lei Zhang 008 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Coordinated Model Pruning and Mapping Framework for RRAM-Based DNN Accelerators. - Songyun Qu; Bing Li 017; Shixin Zhao; Lei Zhang 008; Ying Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses. - Cheng Chu; Cheng Liu 008; Dawen Xu 002; Ying Wang 001; Tao Luo 014; Huawei Li 001; Xiaowei Li 001 (ACM Trans. Design Autom. Electr. Syst., 2023)

Statistical Modeling of Soft Error Influence on Neural Networks. - Haitong Huang; Xinghua Xue; Cheng Liu 008; Ying Wang 001; Tao Luo 014; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance. - Xinghua Xue; Cheng Liu 008; Bo Liu 018; Haitong Huang; Ying Wang 001; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Toward Network-Aware Query Execution Systems in Large Datacenters. - Long Cheng 003; Ying Wang 001; Rutvij H. Jhaveri; Qingle Wang; Ying Mao 001 (IEEE Trans. Netw. Serv. Manag., 2023)

Soft Error Reliability Analysis of Vision Transformers. - Xinghua Xue; Cheng Liu 008; Ying Wang 001; Bing Yang; Tao Luo 014; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Chaos: Function Granularity Runtime Address Layout Space Randomization for Kernel Module. - Zihao Chang; Jihan Lin; Haifeng Sun 004; Runkuang Li; Ying Wang 001; Bin Hu; Xiaofang Zhao; Dejun Jiang 001; Ninghui Sun; Sa Wang (APSys, 2024)

APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction. - Lei Dai; Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ASPDAC, 2024)

Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration. - Fuping Li; Ying Wang 001; Yujie Wang; Mengdi Wang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (ASPDAC, 2024)

CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators. - Songyun Qu; Shixin Zhao; Bing Li 017; Yintao He; Xuyi Cai; Lei Zhang 008; Ying Wang 001 (ASPLOS (2), 2024)

PrimePar: Efficient Spatial-temporal Tensor Partitioning for Large Transformer Model Training. - Haoran Wang 012; Lei Wang 222; Haobo Xu; Ying Wang 001; Yuming Li; Yinhe Han 001 (ASPLOS (3), 2024)

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. - Kaiyan Chang; Kun Wang 055; Nan Yang; Ying Wang 001; Dantong Jin; Wenlong Zhu; Zhirong Chen; Cangyuan Li; Hao Yan; Yunhao Zhou; Zhuoliang Zhao; Yuan Cheng; et al. (DAC, 2024)

Chiplever: Towards Effortless Extension of Chiplet-based System for FHE. - Yibo Du; Ying Wang 001; Bing Li 017; Fuping Li; Shengwen Liang; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (DAC, 2024)

Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration. - Lian Liu; Zhaohui Xu; Yintao He; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (DAC, 2024)

GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction. - Yibo Du; Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (DATE, 2024)

Bit-Trimmer: Ineffectual Bit-Operation Removal for CLM Architecture. - Yintao He; Shixin Zhao; Songyun Qu; Huawei Li 001; Xiaowei Li 001; Ying Wang 001 (DATE, 2024)

HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System. - Shengwen Liang; Ziming Yuan; Ying Wang 001; Dawen Xu 002; Huawei Li 001; Xiaowei Li 001 (DATE, 2024)

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. - Kaiyan Chang; Zhirong Chen; Yunhao Zhou; Wenlong Zhu; Kun Wang 055; Haobo Xu; Cangyuan Li; Mengdi Wang; Shengwen Liang; Huawei Li 001; Yinhe Han 001; Ying Wang 001 (ICCAD, 2024)

AGC: A Unified Architecture for Accelerating K-Nearest Neighbor Graph Construction in Vector Search. - Lei Dai; Ziming Yuan; Wen Li; Shengwen Liang; Kaiwei Zou; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2024)

A visual cortex-inspired edge neuromorphic hardware architecture with on-chip multi-layer STDP learning. - Junxian He; Min Tian; Ying Jiang; Haibing Wang; Tengxiao Wang; Xichuan Zhou; Liyuan Liu; Nanjian Wu; Ying Wang 001; Cong Shi 003 (Comput. Electr. Eng., 2024)

Approximate data mapping in refresh-free DRAM for energy-efficient computing in modern mobile systems. - Sen Li; Hui Jin; Yingke Gao; Ying Wang 001; Shuhong Dai; Yongjun Xu 001; Long Cheng 003 (Comput. Commun., 2024)

GTA: a new General Tensor Accelerator with Better Area Efficiency and Data Reuse. - Chenyang Ai; Lechuan Zhao; Zhijie Huang; Cangyuan Li; Xinan Wang; Ying Wang 001 (CoRR, 2024)

SuperEncoder: Towards Universal Neural Approximate Quantum State Preparation. - Yilun Zhao 002; Bingmeng Wang; Wenle Jiang; Xiwei Pan; Bing Li 017; Yinhe Han 001; Ying Wang 001 (CoRR, 2024)

COMET: Towards Partical W4A4KV4 LLMs Serving. - Lian Liu; Haimeng Ren; Long Cheng 003; Zhaohui Xu; Yudong Pan; Mengdi Wang; Xiaowei Li 001; Yinhe Han 001; Ying Wang 001 (CoRR, 2024)

DRIM-ANN: An Approximate Nearest Neighbor Search Engine based on Commercial DRAM-PIMs. - Mingkai Chen; Tianhua Han; Cheng Liu 008; Shengwen Liang; Kuai Yu; Lei Dai; Ziming Yuan; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (CoRR, 2024)

Discovering Hierarchical Multi-Instance Business Processes From Event Logs. - Cong Liu 012; Ying Wang 001; Lijie Wen 001; Jiujun Cheng; Long Cheng 003; Qingtian Zeng (IEEE Trans. Serv. Comput., 2024)

Advancements in Accelerating Deep Neural Network Inference on AIoT Devices: A Survey. - Long Cheng 003; Yan Gu; Qingzhi Liu; Lei Yang 018; Cheng Liu 008; Ying Wang 001 (IEEE Trans. Sustain. Comput., 2024)

A Deep Reinforcement Learning-Based Preemptive Approach for Cost-Aware Cloud Job Scheduling. - Long Cheng 003; Yue Wang 073; Feng Cheng; Cheng Liu 008; Zhiming Zhao; Ying Wang 001 (IEEE Trans. Sustain. Comput., 2024)

Dynamic WiFi indoor positioning based on the multi-scale metric learning. - Yujie Wang 002; Ying Wang 001; Qingqing Liu; Yong Zhang 044 (Comput. Commun., 2024)

Real-Time Robust Video Object Detection System Against Physical-World Adversarial Attacks. - Husheng Han; Xing Hu 001; Yifan Hao 001; Kaidi Xu; Pucheng Dang; Ying Wang 001; Yongwei Zhao; Zidong Du; Qi Guo 001; Yanzhi Wang; Xishan Zhang; Tianshi Chen 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference. - Lian Liu; Ying Wang 001; Xiandong Zhao; Weiwei Chen; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating. - Mingkai Chen; Cheng Liu 008; Shengwen Liang; Lei He 016; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks. - Yintao He; Bing Li 017; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

High-Parallel In-Memory NTT Engine with Hierarchical Structure and Even-Odd Data Mapping. - Bing Li 017; Huaijun Liu; Yibo Du; Ying Wang 001 (ASP-DAC, 2025)

RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. - Kun Wang 055; Kaiyan Chang; Mengdi Wang; Xingqi Zou; Haobo Xu; Yinhe Han 001; Ying Wang 001 (ASP-DAC, 2025)

PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System. - Yintao He; Haiyu Mao; Christina Giannoula; Mohammad Sadrosadati; Juan Gómez-Luna; Huawei Li 001; Xiaowei Li 001; Ying Wang 001; Onur Mutlu (ASPLOS (2), 2025)

COMET: Towards Practical W4A4KV4 LLMs Serving. - Lian Liu; Long Cheng 003; Haimeng Ren; Zhaohui Xu; Yudong Pan; Mengdi Wang; Xiaowei Li 001; Yinhe Han 001; Ying Wang 001 (ASPLOS (2), 2025)

Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators. - Shixin Zhao; Yuming Li; Bing Li 017; Yintao He; Mengdi Wang; Yinhe Han 001; Ying Wang 001 (ASPLOS (2), 2025)

ATP: Adaptive Threshold Pruning for Efficient Data Encoding in Quantum Neural Networks. - Mohamed Afane; Gabrielle Ebbrecht; Ying Wang 001; Juntao Chen; Junaid Farooq 001 (CVPR, 2025)

Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM. - Lian Liu; Shixin Zhao; Bing Li 017; Haimeng Ren; Zhaohui Xu; Mengdi Wang; Xiaowei Li 001; Yinhe Han 001; Ying Wang 001 (HPCA, 2025)

LAD: Efficient Accelerator for Generative Inference of LLM with Locality Aware Decoding. - Haoran Wang 012; Yuming Li; Haobo Xu; Ying Wang 001; Liqi Liu; Jun Yang 006; Yinhe Han 001 (HPCA, 2025)

NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search. - Ziming Yuan; Lei Dai; Wen Li; Jie Zhang 048; Shengwen Liang; Ying Wang 001; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001; Jiafeng Guo; Peng Wang 037; Renhai Chen; et al. (HPCA, 2025)

Taijigraph: an Out-Of-Core Graph Processing System Enhanced with Computational Storage. - Xinmiao Zhang 004; Cheng Liu 008; Shengwen Liang; Hayden Kwok-Hay So; Ying Wang 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (IPDPS, 2025)

CIT-CTPlacer: An Analytical RDL Chiplet-Terminal Co-Placement Algorithm for Large-Scale 2.5D IC. - Xihao Liang; Yujie Wang; Xupengkai Lu; Lang Feng 001; Jixiang Zhu; Ying Wang 001; Yinhe Han 001 (ISCAS, 2025)

Attar: RRAM-based in-memory attention accelerator with software-hardware co-optimization. - Bing Li 017; Ying Qi; Ying Wang 001; Yinhe Han 001 (Sci. China Inf. Sci., 2025)

APoX-M: Accelerate deep point cloud analysis via adaptive graph construction. - Lei Dai; Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (Integr., 2025)

Deep Reinforcement Learning for Job Scheduling and Resource Management in Cloud Computing: An Algorithm-Level Review. - Yan Gu; Zhaoze Liu; Shuhong Dai; Cong Liu 012; Ying Wang 001; Shen Wang 006; Georgios Theodoropoulos 001; Long Cheng 003 (CoRR, 2025)

RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. - Kun Wang 055; Kaiyan Chang; Mengdi Wang; Xinqi Zou; Haobo Xu; Yinhe Han 001; Ying Wang 001 (CoRR, 2025)

Accelerate Point Cloud Structuring for Deep Neural Networks via Fast Spatial-Searching Tree. - Jinyu Zhan; Shiyu Zou; Wei Jiang 016; Youyuan Zhang; Suidi Peng; Ying Wang 001 (IEEE Trans. Circuits Syst. Video Technol., 2025)

Large Processor Chip Model. - Kaiyan Chang; Mingzhi Chen; Yunji Chen; Zhirong Chen; Dongrui Fan; Junfeng Gong; Nan Guo; Yinhe Han 001; Qinfen Hao; Shuo Hou; Xuanjing Huang 001; Pengwei Jin; et al. (CoRR, 2025)

QiMeng: Fully Automated Hardware and Software Design for Processor Chip. - Rui Zhang 040; Yuanbo Wen; Shuyao Cheng; Di Huang; Shaohui Peng; Jiaming Guo; Pengwei Jin; Jiacheng Zhao; Tianrui Ma; Yaoyu Zhu; Yifan Hao 001; Yongwei Zhao; et al. (CoRR, 2025)

SQUASH: A SWAP-Based Quantum Attack to Sabotage Hybrid Quantum Neural Networks. - Rahul Kumar; Wenqi Wei 001; Ying Mao 001; Junaid Farooq 001; Ying Wang 001; Juntao Chen (CoRR, 2025)

Functional Testing and Repair for ReRAM-Based Deep-Learning Accelerators. - Wen Li; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Kaiwei Zou (IEEE Des. Test, 2025)

Improving DNN Accuracy on MLC PIM via Non-Ideal PIM Device Fine-Tuning. - Hao Lv; Lei Zhang 008; Ying Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

ChipSeek-R1: Generating Human-Surpassing RTL with LLM via Hierarchical Reward-Driven Reinforcement Learning. - Zhirong Chen; Kaiyan Chang; Zhuolin Li; Xinyang He; Chujie Chen; Cangyuan Li; Mengdi Wang; Haobo Xu; Yinhe Han 001; Ying Wang 001 (CoRR, 2025)

MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs. - Chenchen Zhao; Zhengyuan Shi; Xiangyu Wen; Chengjie Liu; Yi Liu; Yunhao Zhou; Yuxiang Zhao; Hefei Feng; Yinan Zhu; Gwok-Waa Wan; Xin Cheng; Weiyu Chen; et al. (CoRR, 2025)

A Visual-Cortex-Mimetic Tiny Neuromorphic Vision Processor Based on Reconfigurable Cortical Neuron Unit. - Mingju Chen; Junxian He; Haibing Wang; Tengxiao Wang; Haoran Gao; Liyuan Liu; Ying Wang 001; Cong Shi 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

DNA: A General Dynamic Neural Network Accelerator. - Lian Liu; Jinxin Yu; Mengdi Wang; Xiaowei Li 001; Yinhe Han 001; Ying Wang 001 (IEEE Trans. Computers, 2025)

In-Situ NAS: A Plug-and-Search Neural Architecture Search Framework Across Hardware Platforms. - Hao Lv; Lei Zhang 008; Ying Wang 001 (IEEE Trans. Computers, 2025)