A digital PLL with a multi-delay coarse-fine TDC. - Ying Wu 003; Ping Lu 002; Pietro Andreani (NORCHIP, 2011)

A 0.13µm CMOS ΔΣ PLL FM transmitter. - Ying Wu 003; Xiaodong Liu; Dawei Ye; Vijay Viswam; Lin Zhu; Ping Lu 002; Dejan Radjen; Henrik Sjöland (NORCHIP, 2011)

A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter. - Ping Lu 002; Ying Wu 003; Pietro Andreani (ISCAS, 2012)

A 0.5ps 1.4mW 50MS/s Nyquist bandwidth time amplifier based two-step flash-ΔΣ time-to-digital converter. - Ying Wu 003; Robert Bogdan Staszewski (EBCCSP, 2016)

A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise. - Ying Wu 003; Mina Shahmohammadi; Yue Chen; Ping Lu 002; Robert Bogdan Staszewski (ESSCIRC, 2016)

A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration. - Ping Lu 002; Ying Wu 003; Pietro Andreani (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase Noise. - Ying Wu 003; Mina Shahmohammadi; Yue Chen; Ping Lu 002; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2017)

A Time-Domain 147fsrms 2.5-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction. - Ying Wu 003; Ping Lu 002; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)