Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001 (ATS, 2008)

Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001; Yu Hu 001 (VTS, 2008)

Selected Crosstalk Avoidance Code for Reliable Network-on-Chip. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001 (J. Comput. Sci. Technol., 2009)

Software-Based Self-Testing of Processors Using Expanded Instructions. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects. - Ying Zhang 040; Huawei Li 001; Yinghua Min; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Automatic Test Program Generation for Out-of-Order Superscalar Processors. - Ying Zhang 040; Ahmed Rezine; Petru Eles; Zebo Peng (Asian Test Symposium, 2012)

Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors. - Ying Zhang 040; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Temperature-aware software-based self-testing for delay faults. - Ying Zhang 040; Zebo Peng; Jianhui Jiang; Huawei Li 001; Masahiro Fujita (DATE, 2015)

Software-based online self-testing of network-on-chip using bounded model checking. - Ying Zhang 040; Krishnendu Chakrabarty; Huawei Li 001; Jianhui Jiang (ITC, 2017)

High-level Fault Diagnosis on network-on-chip using path tracking. - Minhui Ke; Ying Zhang 040; Jianhui Jiang (VLSI-DAT, 2017)

Small Trojan Testing Using Bounded Model Checking. - Ying Zhang 040; Lu Yu; Huawei Li 001; Jianhui Jiang (ITC-Asia, 2018)

Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition. - Ying Zhang 040; Li Ling; Jianhui Jiang; Jie Xiao 003 (J. Electron. Test., 2018)

A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Wafer-Level NoC. - Zhongsheng Chen; Ying Zhang 040; Zebo Peng; Jianhui Jiang (DATE, 2019)

HIT: A Hidden Instruction Trojan Model for Processors. - Jiaqi Zhang; Ying Zhang 040; Huawei Li 001; Jianhui Jiang (DATE, 2020)

Parallel Genetic Algorithm to Extend the Lifespan of Internet of Things in 5G Networks. - Ying Zhang 040; Weihong Yu; Xiaodong Chen; Jianhui Jiang (IEEE Access, 2020)

Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors. - Ying Zhang 040; Krishnendu Chakrabarty; Zebo Peng; Ahmed Rezine; Huawei Li 001; Petru Eles; Jianhui Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-Chip. - Ying Zhang 040; Xinpeng Hong; Zhongsheng Chen; Zebo Peng; Jianhui Jiang (ACM Trans. Design Autom. Electr. Syst., 2021)

BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature. - Ying Zhang 040; Yi Ding; Zebo Peng; Huawei Li 001; Masahiro Fujita; Jianhui Jiang (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-Chip. - Ying Zhang 040; Pengfei Ji; Pan-Wei Zhu; Zebo Peng; Huawei Li 001; Jian-Hui Jiang (J. Comput. Sci. Technol., 2023)

Identifying Reliability High-Correlated Gates of Logic Circuits With Pearson Correlation Coefficient. - Zhanhui Shi; Jie Xiao 003; Jianhui Jiang; Ying Zhang 040; Yuhao Zhou (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis Approach. - Zhanhui Shi; Jie Xiao 003; Jianhui Jiang; Ying Zhang 040; Yuhao Zhou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

On Modeling and Detecting Trojans in Instruction Sets. - Ying Zhang 040; Aodi He; Jiaying Li; Ahmed Rezine; Zebo Peng; Erik Larsson; Tao Yang; Jianhui Jiang; Huawei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Efficient Area and Reliability Optimization Method for MPRM Circuits Based on High-dimensional Genetic Algorithm. - Yuhao Zhou; Jianhui Jiang; Zhenxue He; Ying Zhang 040; Chengcheng Chen; Zhanhui Shi; Wei Zhang 248; Keying Yang (ACM Trans. Design Autom. Electr. Syst., 2025)

Multiobjective Optimization in Logic Synthesis Based on TB-RM Dual Logic. - Yuhao Zhou; Zhen Wang 042; Xiangxue Kong; Hongyang Pan; Zhenxue He; Ying Zhang 040; Jianhui Jiang; Limin Xiao; Xiang Wang 006 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)