An Efficient Compressive Convolutional Network for Unified Object Detection and Image Compression. - Xichuan Zhou; Lang Xu; Shujun Liu; Yingcheng Lin; Lei Zhang 038; Cheng Zhuo (AAAI, 2019)

20, 000-fps Visual Motion Magnification on Pixel-parallel Vision Chip. - Junxian He; Xichuan Zhou; Yingcheng Lin; Chonglei Sun; Cong Shi 003; Nanjian Wu; Gang Luo 003 (ASICON, 2019)

High-speed Classification of AER Data Based on a Low-cost Hardware System. - Jinguo Huang; Yingcheng Lin; Wei He; Xichuan Zhou; Cong Shi 003; Nanjian Wu; Gang Luo 003 (ASICON, 2019)

A High-speed Low-cost CNN Inference Accelerator for Depthwise Separable Convolution. - Yingcheng Lin; Rui Li; Wei He; Xichuan Zhou; Junxian He; Ping Li 042; Ying Jiang; Liyuan Liu; Nanjian Wu; Cong Shi 003 (ICTA, 2020)

A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification. - Wei He; Jinguo Huang; Tengxiao Wang; Yingcheng Lin; Junxian He; Xichuan Zhou; Ping Li 042; Ying Wang 001; Nanjian Wu; Cong Shi 003 (Sensors, 2020)

ICONet: A Lightweight Network with Greater Environmental Adaptivity. - Wei He; Yanmei Huang; Zanhao Fu; Yingcheng Lin (Symmetry, 2020)

A Pixel-Parallel Array Processor without Computational Logic for Computational Image Sensors. - Yingcheng Lin; Rui Li; Wei He; Xichuan Zhou; Junxian He; Ping Li 042; Liyuan Liu; Nanjian Wu; Cong Shi 003 (ICTA, 2021)

CompSNN: A lightweight spiking neural network based on spatiotemporally compressive spike features. - Tengxiao Wang; Cong Shi 003; Xichuan Zhou; Yingcheng Lin; Junxian He; Ping Gan; Ping Li 042; Ying Wang 001; Liyuan Liu; Nanjian Wu; Gang Luo 003 (Neurocomputing, 2021)

An Efficient Ensemble Binarized Deep Neural Network on Chip with Perception-Control Integrated. - Wei He; Dehang Yang; Haoqi Peng; Songhong Liang; Yingcheng Lin (Sensors, 2021)

A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps. - Ling Zhang; Jing Yang 067; Cong Shi 003; Yingcheng Lin; Wei He; Xichuan Zhou; Xu Yang 004; Liyuan Liu; Nanjian Wu (Sensors, 2021)

A Low-Cost High-Speed Object Tracking VLSI System Based on Unified Textural and Dynamic Compressive Features. - Wei He; Jie Zhang; Yingcheng Lin; Xichuan Zhou; Ping Li 042; Liyuan Liu; Nanjian Wu; Cong Shi 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Real-Time FPGA Implementation of Infrared and Visible Image Fusion Using Guided Filter and Saliency Detection. - Ling Zhang; Xuefei Yang; Zhenlong Wan; Dingxin Cao; Yingcheng Lin (Sensors, 2022)

Multi-Scale FPGA-Based Infrared Image Enhancement by Using RGF and CLAHE. - Jialong Liu; Xichuan Zhou; Zhenlong Wan; Xuefei Yang; Wei He; Rulong He; Yingcheng Lin (Sensors, 2023)

STOP: Spatiotemporal Orthogonal Propagation for Weight-Threshold-Leakage Synergistic Training of Deep Spiking Neural Networks. - Haoran Gao; Xichuan Zhou; Yingcheng Lin; Min Tian; Liyuan Liu; Cong Shi 003 (CoRR, 2024)

Ghost Reservoir: A Memory-Efficient Low-Power and Real-Time Neuromorphic Processor of Liquid State Machine With On-Chip Learning. - Cong Shi 003; Xiang Fu; Haibing Wang; Yingcheng Lin; Ying Jiang; Liyuan Liu; Nanjian Wu; Min Tian (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Distribution-modulated binary neural network for image classification. - Yingcheng Lin; Yuxiao Wang; Rui Ding 009; Haijun Liu 001; Xichuan Zhou (Image Vis. Comput., 2025)

MorphBungee-Lite: An Edge Neuromorphic Architecture With Balanced Cross-Core Workloads Based on Layer-Wise Event-Batch Learning/Inference. - Zhengqing Zhong; Haibing Wang; Mingju Chen; Yingcheng Lin; Min Tian; Tengxiao Wang; Liyuan Liu; Cong Shi 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

MorphBungee: A 65-nm 7.2-mm2 27-µJ/Image Digital Edge Neuromorphic Chip With on-Chip 802-Frame/s Multi-Layer Spiking Neural Network Learning. - Tengxiao Wang; Min Tian; Haibing Wang; Zhengqing Zhong; Junxian He; Fang Tang; Xichuan Zhou; Yingcheng Lin; Shuangming Yu; Liyuan Liu; Cong Shi 003 (IEEE Trans. Biomed. Circuits Syst., 2025)

An Edge Neuromorphic Processor With High-Accuracy On-Chip Aggregate-Label Learning. - Guanyu Chen; Mingju Chen; Tengxiao Wang; Haibing Wang; Xiang Fu; Yingcheng Lin; Liyuan Liu; Cong Shi 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A High-Performance RDMA NIC With Ultrahighly Scalable Connections. - Ling Zhang; Xuefei Yang; Zhenlong Wan; Hang Liu; Wei Gu; Pingjing Liu; Qilin Dai; Shanwei Ye; Yingcheng Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)