Transistor and circuit design for 100-200-GHz ICs. - Zach Griffith; Yingda Dong; Dennis W. Scott; Yun Wei; Navin Parthasarathy; Mattias Dahlström; Christoph Kadow; Vamsi Paidi; Mark J. W. Rodwell; Miguel Urteaga; Richard Pierson; Petra Rowell; et al. (IEEE J. Solid State Circuits, 2005)

A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm. - Raul Cernea; Long Pham; Farookh Moogat; Siu Lung Chan; Binh Le; Yan Li; Shouchang Tsao; Taiyuan Tseng; Khanh Nguyen; Jason Li 001; Jayson Hu; Jong Park; et al. (ISSCC, 2008)

A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology. - Raul Cernea; Long Pham; Farookh Moogat; Siu Lung Chan; Binh Le; Yan Li; Shouchang Tsao; Taiyuan Tseng; Khanh Nguyen; Jason Li 001; Jayson Hu; Jonghak Yuh; et al. (IEEE J. Solid State Circuits, 2009)

11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology. - Ryuji Yamashita; Sagar Magia; Tsutomu Higuchi; Kazuhide Yoneya; Toshio Yamamura; Hiroyuki Mizukoshi; Shingo Zaitsu; Minoru Yamashita; Shunichi Toyama; Norihiro Kamae; Juan Lee; Shuo Chen; et al. (ISSCC, 2017)

Distributed Cycling in Charge Trap-Based 3D NAND Arrays: Model and Qualification Tests Implications. - Gianluca Nicosia; Niccolò Righetti; Yingda Dong (IMW, 2023)

Traditional pattern enhancement based on improved singular value decomposition and gamma function in the frequency domain. - Yingda Dong; Chunguang He; Yanping Qin; Yunmei Yuan; Fan Gao; Huaqiong Duo; Ximing Wang (J. Intell. Fuzzy Syst., 2023)

Comprehensive physics-based modeling of post-cycling long-term data retention in 176L 3-D NAND Flash Memories. - Karansingh Thakor; Nikhil Rangarajan; Himanshu Diwakar; Rashmi Saikia; Tarun Samadder; Souvik Mahapatra; Shyam Raghunathan; Yingda Dong (IMW, 2024)

Experimental Segmentation of Vertical Charge Loss Mechanisms in Charge Trap-Based 3D NAND Arrays. - Luca Chiavarone; Gianluca Nicosia; Niccolò Righetti; Yingda Dong (IRPS, 2024)