Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. - Yinhe Han 001; Yongjun Xu 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (Asian Test Symposium, 2003)

Rapid and Energy-Efficient Testing for Embedded Cores. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (Asian Test Symposium, 2004)

Pair Balance-Based Test Scheduling for SOCs. - Yu Hu 001; Yinhe Han 001; Huawei Li 001; Tao Lv 001; Xiaowei Li 001 (Asian Test Symposium, 2004)

Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test. - Yinhe Han 001; Xiaowei Li 001 (ESA/VLSI, 2004)

Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (DFT, 2004)

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (ASP-DAC, 2005)

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. - Yinhe Han 001; Xiaowei Li 001; Shivakumar Swaminathan; Yu Hu 001; Anshuman Chandra (Asian Test Symposium, 2005)

Deterministic and low power BIST based on scan slice overlapping. - Ji Li; Yinhe Han 001; Xiaowei Li 001 (ISCAS (6), 2005)

Validation analysis and test flow optimization of VLSI chip. - Yanzhuo Tan; Yinhe Han 001; Xiaowei Li 001; Feiyin Lu; Yuchuan Chen (ISCAS (6), 2005)

Using MUXs Network to Hide Bunches of Scan Chains. - Yinhe Han 001; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (ISQED, 2005)

SoC Leakage Power Reduction Algorithm by Input Vector Control. - Xiaotao Chang; Dongrui Fan; Yinhe Han 001; Zhimin Zhang 004 (SoC, 2005)

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. - Yinhe Han 001; Yu Hu 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra; Xiaoqing Wen (IEICE Trans. Inf. Syst., 2005)

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. - Yinhe Han 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra (J. Comput. Sci. Technol., 2005)

Test data compression based on clustered random access scan. - Yu Hu 001; Cheng Li; Jia Li 022; Yinhe Han 001; Xiaowei Li 001; Wei Wang; Huawei Li 001; Laung-Terng Wang; Xiaoqing Wen (ATS, 2006)

Fast Packet Classification using Group Bit Vector. - Tong Liu; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (GLOBECOM, 2006)

An on-chip combinational decompressor for reducing test data volume. - Jie Don; Yu Hu 001; Yinhe Han 001; Xiaowei Li 001 (ISCAS, 2006)

Response compaction for system-on-a-chip based on advanced convolutional codes. - Yinhe Han 001; Huawei Li 001; Xiaowei Li 001; Anshuman Chandra (Sci. China Ser. F Inf. Sci., 2006)

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. - Yu Hu 001; Yinhe Han 001; Xiaowei Li 001; Huawei Li 001; Xiaoqing Wen (IEICE Trans. Inf. Syst., 2006)

Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes. - Yinhe Han 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra (IEEE Trans. Instrum. Meas., 2006)

Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic. - Shaohua Lei; Yinhe Han 001; Xiaowei Li 001 (ATS, 2007)

Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment. - Wei Wang; Yu Hu 001; Yinhe Han 001; Xiaowei Li 001; You-Sheng Zhang (J. Comput. Sci. Technol., 2007)

Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. - Yinhe Han 001; Yu Hu 001; Xiaowei Li 001; Huawei Li 001; Anshuman Chandra (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. - Lei Zhang 008; Yinhe Han 001; Qiang Xu 001; Xiaowei Li 001 (DATE, 2008)

BAT: Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Asynchronous Transmission. - Guihai Yan; Yinhe Han 001; Xiaowei Li 001; Hui Liu (IEICE Trans. Electron., 2008)

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. - Song Jin; Yinhe Han 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001; Guihai Yan (Asian Test Symposium, 2009)

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. - Zichu Qi; Hui Liu; Xiangku Li; Da Wang; Yinhe Han 001; Huawei Li 001; Weiwu Hu (Asian Test Symposium, 2009)

A unified online Fault Detection scheme via checking of Stability Violation. - Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (DATE, 2009)

MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency. - Guihai Yan; Yinhe Han 001; Hui Liu; Xiaoyao Liang; Xiaowei Li 001 (ISLPED, 2009)

Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy. - Jianbo Dong; Lei Zhang 008; Yinhe Han 001; Guihai Yan; Xiaowei Li 001 (PRDC, 2009)

A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. - Binzhang Fu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (PRDC, 2009)

A New Post-Silicon Debug Approach Based on Suspect Window. - Jianliang Gao; Yinhe Han 001; Xiaowei Li 001 (VTS, 2009)

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. - Lei Zhang 008; Yinhe Han 001; Qiang Xu 001; Xiaowei Li 001; Huawei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework. - Song Jin; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. - Binzhang Fu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2010)

Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors. - Lei Zhang 008; Yue Yu; Jianbo Dong; Yinhe Han 001; Shangping Ren; Xiaowei Li 001 (DATE, 2010)

Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. - Guihai Yan; Xiaoyao Liang; Yinhe Han 001; Xiaowei Li 001 (ISCA, 2010)

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. - Huawei Li 001; Dawen Xu 002; Yinhe Han 001; Kwang-Ting Cheng; Xiaowei Li 001 (ITC, 2010)

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (PRDC, 2010)

A Novel Post-Silicon Debug Mechanism Based on Suspect Window. - Jianliang Gao; Yinhe Han 001; Xiaowei Li 001 (IEICE Trans. Inf. Syst., 2010)

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power. - Jun Liu; Yinhe Han 001; Xiaowei Li 001 (IEICE Trans. Inf. Syst., 2010)

Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling. - Jianbo Dong; Lei Zhang 008; Yinhe Han 001; Guihai Yan; Xiaowei Li 001 (J. Syst. Archit., 2010)

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip. - Cheng Liu 008; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2011)

A resilient on-chip router design through data path salvaging. - Cheng Liu 008; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2011)

Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC. - Yuanqing Cheng; Lei Zhang 008; Yinhe Han 001; Jun Liu; Xiaowei Li 001 (Asian Test Symposium, 2011)

Wear rate leveling: lifetime enhancement of PRAM with endurance variation. - Jianbo Dong; Lei Zhang 008; Yinhe Han 001; Ying Wang 001; Xiaowei Li 001 (DAC, 2011)

Eliminating data invalidation in debugging multiple-clock chips. - Jianliang Gao; Yinhe Han 001; Xiaowei Li 001 (DATE, 2011)

Flex memory: Exploiting and managing abundant off-chip optical bandwidth. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2011)

An abacus turn model for time/space-efficient reconfigurable routing. - Binzhang Fu; Yinhe Han 001; Jun Ma; Huawei Li 001; Xiaowei Li 001 (ISCA, 2011)

A New Multiple-Round Dimension-Order Routing for Networks-on-Chip. - Binzhang Fu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEICE Trans. Inf. Syst., 2011)

Statistical lifetime reliability optimization considering joint effect of process variation and aging. - Song Jin; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (Integr., 2011)

ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation. - Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Computers, 2011)

MicroFix: Using timing interpolation and delay sensors for power reduction. - Guihai Yan; Yinhe Han 001; Hui Liu; Xiaoyao Liang; Xiaowei Li 001 (ACM Trans. Design Autom. Electr. Syst., 2011)

SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation. - Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems. - Jianliang Gao; Jianxin Wang; Yinhe Han 001; Lei Zhang 008; Xiaowei Li 001 (DATE, 2012)

AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture. - Guihai Yan; Yingmin Li; Yinhe Han 001; Xiaowei Li 001; Minyi Guo; Xiaoyao Liang (HPCA, 2012)

M-IVC: Applying multiple input vectors to co-optimize aging and leakage. - Song Jin; Yinhe Han 001 (Microelectron. J., 2012)

RISO: relaxed network-on-chip isolation for cloud processors. - Hang Lu; Guihai Yan; Yinhe Han 001; Binzhang Fu; Xiaowei Li 001 (DAC, 2013)

SmartCap: user experience-oriented power adaptation for smartphone's application processor. - Xueliang Li 004; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (DATE, 2013)

Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction. - Yinhe Han 001; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ISCAS, 2013)

On predicting NBTI-induced circuit aging by isolating leakage change. - Yinhe Han 001; Song Jin; Jibing Qiu; Qiang Xu 001; Xiaowei Li 001 (ISQED, 2013)

TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design. - Yuanqing Cheng; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (J. Comput. Sci. Technol., 2013)

RevivePath: Resilient Network-on-Chip Design Through Data Path Salvaging of Router. - Yinhe Han 001; Cheng Liu 008; Hang Lu; Wen-Bo Li; Lei Zhang 008; Xiaowei Li 001 (J. Comput. Sci. Technol., 2013)

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs. - Yuanqing Cheng; Lei Zhang 008; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction. - Song Jin; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraints. - Song Jin; Yinhe Han 001; Songwei Pei (ASP-DAC, 2014)

Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-cores. - Jun Ma; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2014)

A low power DRAM refresh control scheme for 3D memory cube. - Ying Wang 001; Yinhe Han 001; Huawei Li 001 (COOL Chips, 2014)

SuperRange: Wide operational range power delivery design for both STV and NTV computing. - Xin He; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (DATE, 2014)

Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube. - Yinhe Han 001; Ying Wang 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2014)

A General-Purpose Many-Accelerator Architecture Based on Dataflow Graph Clustering of Applications. - Peng Chen 004; Lei Zhang 008; Yinhe Han 001; Yunji Chen (J. Comput. Sci. Technol., 2014)

Reinventing Memory System Design for Many-Accelerator Architecture. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001 (J. Comput. Sci. Technol., 2014)

SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor. - Xueliang Li 004; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (ACM Trans. Design Autom. Electr. Syst., 2014)

ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels. - Binzhang Fu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Test-Quality Optimization for Variable $n$ -Detections of Transition Faults. - Dawen Xu 002; Huawei Li 001; Amirali Ghofrani; Kwang-Ting Cheng; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptation. - Hang Lu; Guihai Yan; Yinhe Han 001; Ying Wang 001; Xiaowei Li 001 (ASP-DAC, 2015)

ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing. - Ying Wang 001; Yinhe Han 001; Lei Zhang 008; Huawei Li 001; Xiaowei Li 001 (DAC, 2015)

RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory. - Ying Wang 001; Yinhe Han 001; Cheng Wang; Huawei Li 001; Xiaowei Li 001 (DAC, 2015)

A case of precision-tunable STT-RAM memory design for approximate neural network. - Ying Wang 001; Lili Song; Yinhe Han 001; Yuanqing Cheng; Huawei Li 001; Xiaowei Li 001 (ISCAS, 2015)

On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island. - Song Jin; Songwei Pei; Yinhe Han 001; Huawei Li 001 (VLSI-DAT, 2015)

A signal degradation reduction method for memristor ratioed logic (MRL) gates. - Bosheng Liu; Ying Wang 001; Zhiqiang You; Yinhe Han 001; Xiaowei Li 001 (IEICE Electron. Express, 2015)

RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors. - Hang Lu; Binzhang Fu; Ying Wang 001; Yinhe Han 001; Guihai Yan; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Economizing TSV Resources in 3-D Network-on-Chip Design. - Ying Wang 001; Yinhe Han 001; Lei Zhang 008; Binzhang Fu; Cheng Liu 008; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Data Remapping for Static NUCA in Degradable Chip Multiprocessors. - Ying Wang 001; Lei Zhang 008; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

ACR: Enabling computation reuse for approximate computing. - Xin He; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2016)

C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization. - Lili Song; Ying Wang 001; Yinhe Han 001; Xin Zhao 044; Bosheng Liu; Xiaowei Li 001 (DAC, 2016)

DISCO: a low overhead in-network data compressor for energy-efficient chip multi-processors. - Ying Wang 001; Yinhe Han 001; Jun Zhou 022; Huawei Li 001; Xiaowei Li 001 (DAC, 2016)

DeepBurning: automatic generation of FPGA-based learning accelerators for the neural network family. - Ying Wang 001; Jie Xu; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2016)

PowerCap: Leverage Performance-Equivalent Resource Configurations for power capping. - Faqiang Sun; Huawei Li 001; Yinhe Han 001; Guihai Yan; Jun Ma (IGSC, 2016)

Wide Operational Range Processor Power Delivery Design for Both Super-Threshold Voltage and Near-Threshold Voltage Computing. - Xin He; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (J. Comput. Sci. Technol., 2016)

Statistical energy optimization on voltage-frequency island based MPSoCs in the presence of process variations. - Song Jin; Yinhe Han 001; Songwei Pei (Microelectron. J., 2016)

An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores. - Jun Ma; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Computers, 2016)

A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands. - Song Jin; Songwei Pei; Yinhe Han 001; Huawei Li 001 (ACM Trans. Design Autom. Electr. Syst., 2016)

EcoUp: Towards Economical Datacenter Upgrading. - Guihai Yan; Jun Ma; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Parallel Distributed Syst., 2016)

Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation. - Yinhe Han 001; Jianbo Dong; Kaiheng Weng; Ying Wang 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. - Ying Wang 001; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. - Ying Wang 001; Yinhe Han 001; Huawei Li 001; Lei Zhang 008; Yuanqing Cheng; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

ApproxEye: Enabling approximate computation reuse for microrobotic computer vision. - Xin He; Guihai Yan; Faqiang Sun; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2017)

BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems. - Shiqi Lian; Ying Wang 001; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2017)

CNN-based object detection solutions for embedded heterogeneous multicore SoCs. - Cheng Wang; Ying Wang 001; Yinhe Han 001; Lili Song; Zhenyu Quan; Jiajun Li; Xiaowei Li 001 (ASP-DAC, 2017)

Dadu: Accelerating Inverse Kinematics for High-DOF Robots. - Shiqi Lian; Yinhe Han 001; Ying Wang 001; Yungang Bao; Hang Xiao; Xiaowei Li 001; Ninghui Sun (DAC, 2017)

FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks. - Wenyan Lu; Guihai Yan; Jiajun Li; Shijun Gong; Yinhe Han 001; Xiaowei Li 001 (HPCA, 2017)

Retention-Aware DRAM Assembly and Repair for Future FGR Memories. - Ying Wang 001; Yinhe Han 001; Cheng Wang; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Exploiting the Potential of Computation Reuse Through Approximate Computing. - Xin He; Shuhao Jiang; Wenyan Lu; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Multi Scale Comput. Syst., 2017)

PowerTrader: Enforcing Autonomous Power Management for Future Large-Scale Many-Core Processors. - Hang Lu; Guihai Yan; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Multi Scale Comput. Syst., 2017)

STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. - Lili Song; Ying Wang 001; Yinhe Han 001; Huawei Li 001; Yuanqing Cheng; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

PIMCH: Cooperative memory prefetching in processing-in-memory architecture. - Sheng Xu; Ying Wang 001; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2018)

Dadu-P: a scalable accelerator for robot motion planning in a dynamic environment. - Shiqi Lian; Yinhe Han 001; Xiaoming Chen 003; Ying Wang 001; Hang Xiao (DAC, 2018)

A retrospective evaluation of energy-efficient object detection solutions on embedded devices. - Ying Wang 001; Zhenyu Quan; Jiajun Li; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2018)

See and Think: Disentangling Semantic Scene Completion. - Shice Liu; Yu Hu 001; Yiming Zeng 003; Qiankun Tang; Beibei Jin; Yinhe Han 001; Xiaowei Li 001 (NeurIPS, 2018)

DimRouter: A Multi-Mode Router Architecture for Higher Energy-Proportionality of On-Chip Networks. - Shiqi Lian; Ying Wang 001; Yinhe Han 001 (J. Comput. Sci. Technol., 2018)

CPicker: Leveraging Performance-Equivalent Configurations to Improve Data Center Energy Efficiency. - Faqiang Sun; Guihai Yan; Xin He; Huawei Li 001; Yinhe Han 001 (J. Comput. Sci. Technol., 2018)

RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving. - Yiming Zeng 003; Yu Hu 001; Shice Liu; Jing Ye 001; Yinhe Han 001; Xiaowei Li 001; Ninghui Sun (IEEE Robotics Autom. Lett., 2018)

A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors. - Ying Wang 001; Huawei Li 001; Yinhe Han 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators. - Jiajun Li; Ying Wang 001; Bosheng Liu; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2019)

Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators. - Bosheng Liu; Xiaoming Chen 003; Ying Wang 001; Yinhe Han 001; Jiajun Li; Haobo Xu; Xiaowei Li 001 (ASP-DAC, 2019)

CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems. - Sheng Xu; Xiaoming Chen 003; Ying Wang 001; Yinhe Han 001; Xiaowei Li 001 (ASP-DAC, 2019)

Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques. - Xiaoming Chen 003; Longxiang Yin; Bosheng Liu; Yinhe Han 001 (DAC, 2019)

System-level hardware failure prediction using deep learning. - Xiaoyi Sun; Krishnendu Chakrabarty; Ruirui Huang; Yiquan Chen; Bing Zhao; Hai Cao; Yinhe Han 001; Xiaoyao Liang; Li Jiang 002 (DAC, 2019)

ACG-Engine: An Inference Accelerator for Content Generative Neural Networks. - Haobo Xu; Ying Wang 001; Yujie Wang; Jiajun Li; Bosheng Liu; Yinhe Han 001 (ICCAD, 2019)

FeMAT: Exploring In-Memory Processing in Multifunctional FeFET-Based Memory Array. - Xiaoyu Zhang 009; Xiaoming Chen 003; Yinhe Han 001 (ICCD, 2019)

Implementation of Parametric Hardware Trojan in FPGA. - Yipei Yang; Jing Ye 001; Xiaowei Li 001; Yinhe Han 001; Huawei Li 001; Yu Hu 001 (ITC-Asia, 2019)

China Test Conference (CTC) - Extending the Global Test Forum to China. - Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (ITC, 2019)

PIMSim: A Flexible and Detailed Processing-in-Memory Simulator. - Sheng Xu; Xiaoming Chen 003; Ying Wang 001; Yinhe Han 001; Xuehai Qian; Xiaowei Li 001 (IEEE Comput. Archit. Lett., 2019)

Accelerating DNN-based 3D point cloud processing for mobile computing. - Bosheng Liu; Xiaoming Chen 003; Yinhe Han 001; Jiajun Li; Haobo Xu; Xiaowei Li 001 (Sci. China Inf. Sci., 2019)

Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator. - Shichang Zhang; Ying Wang 001; Xiaoming Chen 003; Yinhe Han 001; Yujie Wang; Xiaowei Li 001 (IEICE Electron. Express, 2019)

Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs. - Xiaoming Chen 003; Kai Ni 004; Michael T. Niemier; Yinhe Han 001; Suman Datta; Xiaobo Sharon Hu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

moDNN: Memory Optimal Deep Neural Network Training on Graphics Processing Units. - Xiaoming Chen 003; Danny Ziyi Chen; Yinhe Han 001; Xiaobo Sharon Hu (IEEE Trans. Parallel Distributed Syst., 2019)

GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks. - Zhao Wang; Yijin Guan; Guangyu Sun 003; Dimin Niu; Yuhao Wang 002; Hongzhong Zheng; Yinhe Han 001 (ACA, 2020)

Search-free Accelerator for Sparse Convolutional Neural Networks. - Bosheng Liu; Xiaoming Chen 003; Yinhe Han 001; Ying Wang 001; Jiajun Li; Haobo Xu; Xiaowei Li 001 (ASP-DAC, 2020)

Exploring Spatial-Temporal Multi-Frequency Analysis for High-Fidelity and Temporal-Consistency Video Prediction. - Beibei Jin; Yu Hu 001; Qiankun Tang; Jingyu Niu; Zhiping Shi 002; Yinhe Han 001; Xiaowei Li 001 (CVPR, 2020)

PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture. - Chaoqun Chu; Yanzhi Wang; Yilong Zhao; Xiaolong Ma; Shaokai Ye; Yunyan Hong; Xiaoyao Liang; Yinhe Han 001; Li Jiang 002 (DAC, 2020)

An Efficient Deep Learning Accelerator for Compressed Video Analysis. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Yinhe Han 001; Xiaowei Li 001 (DAC, 2020)

Dadu-CD: Fast and Efficient Processing-in-Memory Accelerator for Collision Detection. - Yuxin Yang 002; Xiaoming Chen 003; Yinhe Han 001 (DAC, 2020)

TUPIM: A Transparent and Universal Processing-in-Memory Architecture for Unmodified Binaries. - Sheng Xu; Xiaoming Chen 003; Xuehai Qian; Yinhe Han 001 (ACM Great Lakes Symposium on VLSI, 2020)

Accelerating RRT Motion Planning Using TCAM. - Yuxin Yang 002; Shiqi Lian; Xiaoming Chen 003; Yinhe Han 001 (ACM Great Lakes Symposium on VLSI, 2020)

Communication Lower Bound in Convolution Accelerators. - Xiaoming Chen 003; Yinhe Han 001; Yu Wang 002 (HPCA, 2020)

DaDu Series - Fast and Efficient Robot Accelerators. - Yinhe Han 001; Yuxin Yang 002; Xiaoming Chen 003; Shiqi Lian (ICCAD, 2020)

Two-Stage Safe Reinforcement Learning for High-Speed Autonomous Racing. - Jingyu Niu; Yu Hu 001; Beibei Jin; Yinhe Han 001; Xiaowei Li 001 (SMC, 2020)

Swallow: A Versatile Accelerator for Sparse Neural Networks. - Bosheng Liu; Xiaoming Chen 003; Yinhe Han 001; Haobo Xu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Architecting Effectual Computation for Machine Learning Accelerators. - Hang Lu; Mingzhe Zhang; Yinhe Han 001; Qi Wang 025; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

DDSAS: Dynamic and Differentiable Space-Architecture Search. - Longxing Yang; Yu Hu 001; Shun Lu 001; Zihao Sun; Jilin Mei; Yiming Zeng 003; Zhiping Shi 002; Yinhe Han 001; Xiaowei Li 001 (ACML, 2021)

FePIM: Contention-Free In-Memory Computing Based on Ferroelectric Field-Effect Transistors. - Xiaoming Chen 003; Yuping Wu; Yinhe Han 001 (ASP-DAC, 2021)

F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM. - Bosheng Liu; Zhuoshen Jiang; Jigang Wu; Xiaoming Chen 003; Yinhe Han 001; Peng Liu 045 (DAC, 2021)

BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory System. - Tao Song; Xiaoming Chen 003; Xiaoyu Zhang 009; Yinhe Han 001 (DAC, 2021)

Eliminating Iterations of Iterative Methods: Solving Large-Scale Sparse Linear System in O(1) with RRAM-based In-Memory Accelerator. - Tao Song; Xiaoming Chen 003; Yinhe Han 001 (ACM Great Lakes Symposium on VLSI, 2021)

KFS-LIO: Key-Feature Selection for Lightweight Lidar Inertial Odometry. - Wei Li 235; Yu Hu 001; Yinhe Han 001; Xiaowei Li 001 (ICRA, 2021)

CoPIM: A Concurrency-aware PIM Workload Offloading Architecture for Graph Applications. - Liang Yan; Mingzhe Zhang; Rujia Wang; Xiaoming Chen 003; Xingqi Zou; Xiaoyang Lu; Yinhe Han 001; Xian-He Sun (ISLPED, 2021)

RRAM-based Analog In-Memory Computing : Invited Paper. - Xiaoming Chen 003; Tao Song; Yinhe Han 001 (NANOARCH, 2021)

Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology. - Xingqi Zou; Sheng Xu; Xiaoming Chen 003; Liang Yan; Yinhe Han 001 (Sci. China Inf. Sci., 2021)

Fault Modeling and Efficient Testing of Memristor-Based Memory. - Peng Liu 045; Zhiqiang You; Jigang Wu; Bosheng Liu; Yinhe Han 001; Krishnendu Chakrabarty (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Dadu-Eye: A 5.3 TOPS/W, 30 fps/1080p High Accuracy Stereo Vision Accelerator. - Feng Min; Haobo Xu; Ying Wang 001; Yujie Wang; Jiajun Li; Xingqi Zou; Bei Li; Yinhe Han 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Integrating Two Logics Into One Crossbar Array for Logic Gate Design. - Lian Yao; Peng Liu 045; Jigang Wu; Yinhe Han 001; Yuehang Zhong; Zhiqiang You (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory. - Peng Liu 045; Zhiqiang You; Jigang Wu; Michael Elimu; Weizheng Wang 002; Shuo Cai; Yinhe Han 001 (IEEE Trans. Emerg. Top. Comput., 2021)

Design and Analysis of Energy-Efficient Dynamic Range Approximate Logarithmic Multipliers for Machine Learning. - Peipei Yin; Chenghua Wang; Haroon Waris; Weiqiang Liu 001; Yinhe Han 001; Fabrizio Lombardi (IEEE Trans. Sustain. Comput., 2021)

Solving Least-Squares Fitting in $O(1)$ Using RRAM-based Computing-in-Memory Technique. - Xiaoming Chen 003; Yinhe Han 001 (ASP-DAC, 2022)

Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems. - Zerun Li; Xiaoming Chen 003; Yinhe Han 001 (ASP-DAC, 2022)

FeMIC: Multi-Operands in-Memory Computing Based on FeFETs. - Rui Liu; Xiaoyu Zhang 009; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (ASP-DAC, 2022)

GraphRing: an HMC-ring based graph processing framework with optimized data movement. - Zerun Li; Xiaoming Chen 003; Yinhe Han 001 (DAC, 2022)

Energy-Efficient In-SRAM Accumulation for CMOS-based CNN Accelerators. - Wanqian Li; Yinhe Han 001; Xiaoming Chen 003 (ACM Great Lakes Symposium on VLSI, 2022)

P3S: A High Accuracy Probabilistic Prediction Processing System for CNN Acceleration. - Hang Xiao; Haobo Xu; Xiaoming Chen 003; Yujie Wang; Yinhe Han 001 (ACM Great Lakes Symposium on VLSI, 2022)

AIC-Bench: Workload Selection Methodology for Benchmarking AI Chips. - Zhenyu Quan; Xiaoming Chen 003; Yinhe Han 001 (HPCC/DSS/SmartCity/DependSys, 2022)

PME: Processing-in-memory Masking and Encoding for Secure NVM. - Zhiwen Xie; Yinhe Han 001; Xiaoming Chen 003 (HPCC/DSS/SmartCity/DependSys, 2022)

GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. - Fuping Li; Ying Wang 001; Yuanqing Cheng; Yujie Wang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2022)

AGNAS: Attention-Guided Micro and Macro-Architecture Search. - Zihao Sun; Yu Hu 001; Shun Lu 001; Longxing Yang; Jilin Mei; Yinhe Han 001; Xiaowei Li 001 (ICML, 2022)

Searching for BurgerFormer with Micro-Meso-Macro Space Design. - Longxing Yang; Yu Hu 001; Shun Lu 001; Zihao Sun; Jilin Mei; Yinhe Han 001; Xiaowei Li 001 (ICML, 2022)

Closing the Dynamics Gap via Adversarial and Reinforcement Learning for High-Speed Racing. - Jingyu Niu; Yu Hu 001; Wei Li 235; Guangyan Huang; Yinhe Han 001; Xiaowei Li 001 (IJCNN, 2022)

DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture. - Xuyi Cai; Ying Wang 001; Xiaohan Ma; Yinhe Han 001; Lei Zhang 008 (MICRO, 2022)

LINAC: A Spatially Linear Accelerator for Convolutional Neural Networks. - Hang Xiao; Haobo Xu; Ying Wang 001; Yujie Wang; Yinhe Han 001 (IEEE Comput. Archit. Lett., 2022)

Survey on chiplets: interface, interconnect and integration methodology. - Xiaohan Ma; Ying Wang 001; Yujie Wang; Xuyi Cai; Yinhe Han 001 (CCF Trans. High Perform. Comput., 2022)

Dadu-SV: Accelerate Stereo Vision Processing on NPU. - Feng Min; Ying Wang 001; Haobo Xu; Junpei Huang; Yujie Wang; Xingqi Zou; Meixuan Lu; Yinhe Han 001 (IEEE Embed. Syst. Lett., 2022)

Fast and High-Accuracy Approximate MAC Unit Design for CNN Computing. - Hang Xiao; Haobo Xu; Xiaoming Chen 003; Yujie Wang; Yinhe Han 001 (IEEE Embed. Syst. Lett., 2022)

STC-NAS: Fast neural architecture search with source-target consistency. - Zihao Sun; Yu Hu 001; Longxing Yang; Shun Lu 001; Jilin Mei; Yinhe Han 001; Xiaowei Li 001 (Neurocomputing, 2022)

Reconfiguration algorithms for synchronous communication on switch based degradable arrays. - Yalan Wu; Jigang Wu; Peng Liu 045; Yinhe Han 001; Thambipillai Srikanthan (Parallel Comput., 2022)

Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals. - Weidong Cao 001; Yilong Zhao; Adith Boloor; Yinhe Han 001; Xuan Zhang 001; Li Jiang 002 (IEEE Trans. Computers, 2022)

Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial Learning. - Weiwei Chen; Ying Wang 001; Ying Xu; Chengsi Gao; Yinhe Han 001; Lei Zhang 008 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Search-Free Inference Acceleration for Sparse Convolutional Neural Networks. - Bosheng Liu; Xiaoming Chen 003; Yinhe Han 001; Jigang Wu; Liang Chang 003; Peng Liu 045; Haobo Xu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture. - Xiaoyu Zhang 009; Rui Liu; Tao Song; Yuxin Yang 002; Yinhe Han 001; Xiaoming Chen 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Toward Efficient Computing for Robotics: From a Circuit and System View. - Haobo Xu; Yuxin Yang 002; Feng Min; Junpei Huang; Xiaoming Chen 003; Yinhe Han 001; Ninghui Sun (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Load Balance Guaranteed Vehicle-to-Vehicle Computation Offloading for Min-Max Fairness in VANETs. - Yalan Wu; Jigang Wu; Long Chen 006; Jiaquan Yan; Yinhe Han 001 (IEEE Trans. Intell. Transp. Syst., 2022)

Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing Approach. - Bosheng Liu; Hongyi Liang; Jigang Wu; Xiaoming Chen 003; Peng Liu 045; Yinhe Han 001 (ASP-DAC, 2023)

APPEND: Rethinking ASIP Synthesis in the Era of AI. - Cangyuan Li; Ying Wang 001; Huawei Li 001; Yinhe Han 001 (DAC, 2023)

PIMCOMP: A Universal Compilation Framework for Crossbar-based PIM DNN Accelerators. - Xiaotian Sun; Xinyu Wang; Wanqian Li; Lei Wang 222; Yinhe Han 001; Xiaoming Chen 003 (DAC, 2023)

FSPA: An FeFET-based Sparse Matrix-Dense Vector Multiplication Accelerator. - Xiaoyu Zhang 009; Zerun Li; Rui Liu; Xiaoming Chen 003; Yinhe Han 001 (DAC, 2023)

Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer Heterogeneity. - Chengsi Gao; Ying Wang 001; Cheng Liu 008; Mengdi Wang; Weiwei Chen; Yinhe Han 001; Lei Zhang 008 (DATE, 2023)

ENASA: Towards Edge Neural Architecture Search based on CIM acceleration. - Shixin Zhao; Songyun Qu; Ying Wang 001; Yinhe Han 001 (DATE, 2023)

CTA: Hardware-Software Co-design for Compressed Token Attention Mechanism. - Haoran Wang 012; Haobo Xu; Ying Wang 001; Yinhe Han 001 (HPCA, 2023)

Meltrix: A RRAM-Based Polymorphic Architecture Enhanced by Function Synthesis. - Boyu Long; Libo Shen; Xiaoyu Zhang 009; Yinhe Han 001; Xian-He Sun; Xiaoming Chen 003 (ICCAD, 2023)

LIM-GEN: A Data-Guided Framework for Automated Generation of Heterogeneous Logic-in-Memory Architecture. - Libo Shen; Boyu Long; Rui Liu; Xiaoyu Zhang 009; Yinhe Han 001; Xiaoming Chen 003 (ICCAD, 2023)

Full State Quantum Circuit Simulation Beyond Memory Limit. - Yilun Zhao 002; Yu Chen; He Li; Ying Wang 001; Kaiyan Chang; Bingmeng Wang; Bing Li 017; Yinhe Han 001 (ICCAD, 2023)

PANG: A Pattern-Aware GCN Accelerator for Universal Graphs. - Yibo Du; Ying Wang 001; Shengwen Liang; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (ICCD, 2023)

Hardware-Software Co-Design for Content-Based Sparse Attention. - Rui Tang; Xiaoyu Zhang 009; Rui Liu; Zhejian Luo; Xiaoming Chen 003; Yinhe Han 001 (ICCD, 2023)

Dadu-RBD: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines. - Yuxin Yang 002; Xiaoming Chen 003; Yinhe Han 001 (MICRO, 2023)

Depth-NeuS: Neural Implicit Surfaces Learning for Multi-view Reconstruction Based on Depth Information Optimization. - Hanqi Jiang; Cheng Zeng; Runnan Chen; Shuai Liang; Yinhe Han 001; Yichao Gao; Conglin Wang (CoRR, 2023)

ChipGPT: How far are we from natural language hardware design. - Kaiyan Chang; Ying Wang 001; Haimeng Ren; Mengdi Wang; Shengwen Liang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2023)

RBDCore: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines. - Yuxin Yang 002; Xiaoming Chen 003; Yinhe Han 001 (CoRR, 2023)

IVP: An Intelligent Video Processing Architecture for Video Streaming. - Chengsi Gao; Ying Wang 001; Yinhe Han 001; Weiwei Chen; Lei Zhang 008 (IEEE Trans. Computers, 2023)

FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing. - Rui Liu; Xiaoyu Zhang 009; Zhiwen Xie; Xinyu Wang; Zerun Li; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Frequency-Domain Inference Acceleration for Convolutional Neural Networks Using ReRAMs. - Bosheng Liu; Zhuoshen Jiang; Yalan Wu; Jigang Wu; Xiaoming Chen 003; Peng Liu 045; Qingguo Zhou; Yinhe Han 001 (IEEE Trans. Parallel Distributed Syst., 2023)

Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration. - Fuping Li; Ying Wang 001; Yujie Wang; Mengdi Wang; Yinhe Han 001; Huawei Li 001; Xiaowei Li 001 (ASPDAC, 2024)

ORIANNA: An Accelerator Generation Framework for Optimization-based Robotic Applications. - Yuhui Hao; Yiming Gan; Bo Yu 014; Qiang Liu 011; Yinhe Han 001; Zishen Wan; Shaoshan Liu (ASPLOS (2), 2024)

ACES: Accelerating Sparse Matrix Multiplication with Adaptive Execution Flow and Concurrency-Aware Cache Optimizations. - Xiaoyang Lu; Boyu Long; Xiaoming Chen 003; Yinhe Han 001; Xian-He Sun (ASPLOS (3), 2024)

PrimePar: Efficient Spatial-temporal Tensor Partitioning for Large Transformer Model Training. - Haoran Wang 012; Lei Wang 222; Haobo Xu; Ying Wang 001; Yuming Li; Yinhe Han 001 (ASPLOS (3), 2024)

Benchmarking and Optimizing Federated Learning with Hardware-related Metrics. - Kai Pan; Yapeng Tian; Yinhe Han 001; Yiming Gan (BMVC, 2024)

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. - Kaiyan Chang; Kun Wang 055; Nan Yang; Ying Wang 001; Dantong Jin; Wenlong Zhu; Zhirong Chen; Cangyuan Li; Hao Yan; Yunhao Zhou; Zhuoliang Zhao; Yuan Cheng; et al. (DAC, 2024)

Chiplever: Towards Effortless Extension of Chiplet-based System for FHE. - Yibo Du; Ying Wang 001; Bing Li 017; Fuping Li; Shengwen Liang; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (DAC, 2024)

Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration. - Lian Liu; Zhaohui Xu; Yintao He; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (DAC, 2024)

GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction. - Yibo Du; Shengwen Liang; Ying Wang 001; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (DATE, 2024)

PIMSYN: Synthesizing Processing-in-Memory CNN Accelerators. - Wanqian Li; Xiaotian Sun; Xinyu Wang; Lei Wang 222; Yinhe Han 001; Xiaoming Chen 003 (DATE, 2024)

PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators. - Xinyu Wang; Xiaotian Sun; Yinhe Han 001; Xiaoming Chen 003 (DATE, 2024)

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. - Kaiyan Chang; Zhirong Chen; Yunhao Zhou; Wenlong Zhu; Kun Wang 055; Haobo Xu; Cangyuan Li; Mengdi Wang; Shengwen Liang; Huawei Li 001; Yinhe Han 001; Ying Wang 001 (ICCAD, 2024)

MemSort: In-Memory Sorting Architecture. - Rui Liu; Xiaoyu Zhang 009; Xinyu Wang; Feng Min; Zhejian Luo; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (ICCD, 2024)

AceMiner: Accelerating Graph Pattern Matching using PIM with Optimized Cache System. - Liang Yan; Xiaoyang Lu; Xiaoming Chen 003; Sheng Xu; Xingqi Zou; Yinhe Han 001; Xian-He Sun (ICCD, 2024)

Depth-NeuS: Neural Implicit Surfaces Learning for Multi-view Reconstruction Based on Depth Information Optimization. - Siqi Wen; Hanqi Jiang; Cheng Zeng; Runnan Chen; Jidong Yuan; Shuai Liang; Yinhe Han 001 (ICIC (5), 2024)

HEX-SIM: Evaluating Multi-modal Large Language Models on Multi-chiplet NPUs. - Xinquan Lin; Haobo Xu; Yinhe Han 001; Yiming Gan (IISWC, 2024)

Accelerating Frequency-domain Convolutional Neural Networks Inference using FPGAs. - Yi Chen; Bosheng Liu; Yongqi Xu; Jigang Wu; Xiaoming Chen 003; Peng Liu 045; Qingguo Zhou; Yinhe Han 001 (ISCAS, 2024)

TMiner: A Vertex-Based Task Scheduling Architecture for Graph Pattern Mining. - Zerun Li; Xiaoming Chen 003; Yinhe Han 001 (MICRO, 2024)

JANM-IK: Jacobian Argumented Nelder-Mead Algorithm for Inverse Kinematics and its Hardware Acceleration. - Yuxin Yang 002; Xiaoming Chen 003; Yinhe Han 001 (IEEE Comput. Archit. Lett., 2024)

Corki: Enabling Real-time Embodied AI Robots via Algorithm-Architecture Co-Design. - Yiyang Huang; Yuhui Hao; Bo Yu 014; Feng Yan; Yuxin Yang 002; Feng Min; Yinhe Han 001; Lin Ma 002; Shaoshan Liu; Qiang Liu 011; Yiming Gan (CoRR, 2024)

SuperEncoder: Towards Universal Neural Approximate Quantum State Preparation. - Yilun Zhao 002; Bingmeng Wang; Wenle Jiang; Xiwei Pan; Bing Li 017; Yinhe Han 001; Ying Wang 001 (CoRR, 2024)

KARMA: Augmenting Embodied AI Agents with Long-and-short Term Memory Systems. - Zixuan Wang; Bo Yu 014; Junzhe Zhao; Wenhao Sun; Sai Hou; Shuai Liang; Xing Hu; Yinhe Han 001; Yiming Gan (CoRR, 2024)

BitQ: Tailoring Block Floating Point Precision for Improved DNN Efficiency on Resource-Constrained Devices. - Yongqi Xu; Yujian Lee; Gao Yi; Bosheng Liu; Yucong Chen; Peng Liu 045; Jigang Wu; Xiaoming Chen 003; Yinhe Han 001 (CoRR, 2024)

COMET: Towards Partical W4A4KV4 LLMs Serving. - Lian Liu; Haimeng Ren; Long Cheng 003; Zhaohui Xu; Yudong Pan; Mengdi Wang; Xiaowei Li 001; Yinhe Han 001; Ying Wang 001 (CoRR, 2024)

DaDu-E: Rethinking the Role of Large Language Model in Robotic Computing Pipeline. - Wenhao Sun; Sai Hou; Zixuan Wang; Bo Yu 014; Shaoshan Liu; Xu Yang; Shuai Liang; Yiming Gan; Yinhe Han 001 (CoRR, 2024)

Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators. - Wanqian Li; Yinhe Han 001; Xiaoming Chen 003 (ACM Trans. Design Autom. Electr. Syst., 2024)

An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference. - Lian Liu; Ying Wang 001; Xiandong Zhao; Weiwei Chen; Huawei Li 001; Xiaowei Li 001; Yinhe Han 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

GAS: General-Purpose In-Memory-Computing Accelerator for Sparse Matrix Multiplication. - Xiaoyu Zhang 009; Zerun Li; Rui Liu; Xiaoming Chen 003; Yinhe Han 001 (IEEE Trans. Computers, 2024)

FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer. - Bo Jiao; Lei Xu; Xinyu Yu; Haitao Yang; Haozhe Zhu; Yu Wang; Jundong Zhu; Dexin Wen; Lingli Wang; Jun Tao 001; Chixiao Chen; Yinhe Han 001; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Crypto-DSEDA: A Domain-Specific EDA Flow for CiM-Based Cryptographic Accelerators. - Rui Liu; Zerun Li; Xiaoyu Zhang 009; Wanqian Li; Libo Shen; Rui Tang; Zhejian Luo; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (IEEE Des. Test, 2024)

RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. - Kun Wang 055; Kaiyan Chang; Mengdi Wang; Xingqi Zou; Haobo Xu; Yinhe Han 001; Ying Wang 001 (ASP-DAC, 2025)

COMET: Towards Practical W4A4KV4 LLMs Serving. - Lian Liu; Long Cheng 003; Haimeng Ren; Zhaohui Xu; Yudong Pan; Mengdi Wang; Xiaowei Li 001; Yinhe Han 001; Ying Wang 001 (ASPLOS (2), 2025)

Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators. - Shixin Zhao; Yuming Li; Bing Li 017; Yintao He; Mengdi Wang; Yinhe Han 001; Ying Wang 001 (ASPLOS (2), 2025)

Aphelios: A Selective Lock-step Neural Processing Unit Design. - Wenhao Sun; Yiming Gan; Yuhui Hao; Yinhe Han 001 (ACM Great Lakes Symposium on VLSI, 2025)

Concurrency-Aware Cache Miss Cost Prediction with Perceptron Learning. - Yuping Wu; Xiaoyang Lu; Xiaoming Chen 003; Yinhe Han 001; Xian-He Sun (ACM Great Lakes Symposium on VLSI, 2025)

Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM. - Lian Liu; Shixin Zhao; Bing Li 017; Haimeng Ren; Zhaohui Xu; Mengdi Wang; Xiaowei Li 001; Yinhe Han 001; Ying Wang 001 (HPCA, 2025)

LAD: Efficient Accelerator for Generative Inference of LLM with Locality Aware Decoding. - Haoran Wang 012; Yuming Li; Haobo Xu; Ying Wang 001; Liqi Liu; Jun Yang 006; Yinhe Han 001 (HPCA, 2025)

Dadu-Corki: Algorithm-Architecture Co-Design for Embodied AI-powered Robotic Manipulation. - Yiyang Huang; Yuhui Hao; Bo Yu 014; Feng Yan; Yuxin Yang 002; Feng Min; Yinhe Han 001; Lin Ma 002; Shaoshan Liu; Qiang Liu 011; Yiming Gan (ISCA, 2025)

CIT-CTPlacer: An Analytical RDL Chiplet-Terminal Co-Placement Algorithm for Large-Scale 2.5D IC. - Xihao Liang; Yujie Wang; Xupengkai Lu; Lang Feng 001; Jixiang Zhu; Ying Wang 001; Yinhe Han 001 (ISCAS, 2025)

In-Memory Computing Accelerator for Iterative Linear Algebra Solvers. - Rui Liu; Zerun Li; Xiaoyu Zhang 009; Xiaoming Chen 003; Yinhe Han 001; Minghua Tang (IEEE Comput. Archit. Lett., 2025)

Pyramid: Accelerating LLM Inference With Cross-Level Processing-in-Memory. - Liang Yan; Xiaoyang Lu; Xiaoming Chen 003; Yinhe Han 001; Xian-He Sun (IEEE Comput. Archit. Lett., 2025)

Attar: RRAM-based in-memory attention accelerator with software-hardware co-optimization. - Bing Li 017; Ying Qi; Ying Wang 001; Yinhe Han 001 (Sci. China Inf. Sci., 2025)

RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. - Kun Wang 055; Kaiyan Chang; Mengdi Wang; Xinqi Zou; Haobo Xu; Yinhe Han 001; Ying Wang 001 (CoRR, 2025)

PIPECIM: Energy-Efficient Pipelined Computing-in-Memory Computation Engine With Sparsity-Aware Technique. - Yuanbo Wang; Liang Chang 002; Jingke Wang; Pan Zhao; Jiahao Zeng; Xin Zhao 044; Wuyang Hao; Liang Zhou; Haining Tan; Yinhe Han 001; Jun Zhou 017 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing. - Zerun Li; Xiaoming Chen 003; Yuxin Yang 002; Feng Min; Xiaoyu Zhang 009; Yinhe Han 001 (IEEE Trans. Computers, 2025)

PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators. - Xiaotian Sun; Xinyu Wang; Wanqian Li; Yinhe Han 001; Xiaoming Chen 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

HEAT: Efficient Vision Transformer Accelerator With Hybrid-Precision Quantization. - Pan Zhao; Donghui Xue; Licheng Wu; Liang Chang 002; Haining Tan; Yinhe Han 001; Jun Zhou 017 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Large Processor Chip Model. - Kaiyan Chang; Mingzhi Chen; Yunji Chen; Zhirong Chen; Dongrui Fan; Junfeng Gong; Nan Guo; Yinhe Han 001; Qinfen Hao; Shuo Hou; Xuanjing Huang 001; Pengwei Jin; et al. (CoRR, 2025)

ChipSeek-R1: Generating Human-Surpassing RTL with LLM via Hierarchical Reward-Driven Reinforcement Learning. - Zhirong Chen; Kaiyan Chang; Zhuolin Li; Xinyang He; Chujie Chen; Cangyuan Li; Mengdi Wang; Haobo Xu; Yinhe Han 001; Ying Wang 001 (CoRR, 2025)

DNA: A General Dynamic Neural Network Accelerator. - Lian Liu; Jinxin Yu; Mengdi Wang; Xiaowei Li 001; Yinhe Han 001; Ying Wang 001 (IEEE Trans. Computers, 2025)

Re-Meltrix: A Reconfigurable Processing-in-Memory Architecture Based on RRAM and Function Synthesis. - Boyu Long; Yinhe Han 001; Xian-He Sun; Xiaoming Chen 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)