A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing. - Limin Jiang; Yi Shi 004; Haiqin Hu; Qingyu Deng; Siyi Xu; Yintao Liu 001; Feng Yuan; Si Wang; Yihao Shen; Fangfang Ye; Shan Cao 001; Zhiyuan Jiang (CoRR, 2024)

A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing. - Limin Jiang; Yi Shi 004; Yintao Liu 001; Qingyu Deng; Siyi Xu; Yihao Shen; Fangfang Ye; Shan Cao 001; Zhiyuan Jiang (ASP-DAC, 2025)

Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP). - Siyi Xu; Limin Jiang; Yintao Liu 001; Yihao Shen; Yi Shi 004; Shan Cao 001; Zhiyuan Jiang (LCTES, 2025)

(Artifact) Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP). - Siyi Xu; Limin Jiang; Yintao Liu 001; Yihao Shen; Yi Shi 004; Shan Cao 001; Zhiyuan Jiang (Zenodo, 2025)

(Artifact) Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP). - Siyi Xu; Limin Jiang; Yintao Liu 001; Yihao Shen; Yi Shi 004; Shan Cao 001; Zhiyuan Jiang (Zenodo, 2025)

A Heterogeneous CNN Compilation Framework for RISC-V CPU and NPU Integration Based on ONNX-MLIR. - Shan Cao 001; Meiling Yang; Yintao Liu 001; Yu Li 051; Beining Zhao 001; Xinyu Chen 007; Zhiyuan Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Venus: A RISC-V Domain Specific Architecture Towards Integrated AI and Wireless Baseband Processing for 6G Edge Intelligence. - Zhiyuan Jiang; Yi Shi 004; Limin Jiang; Haiqin Hu; Qingyu Deng; Siyi Xu; Yintao Liu 001; Feng Yuan; Shan Cao 001; Sheng Zhou 001 (IEEE Wirel. Commun., 2025)

Late Breaking Results: A Power-Efficient RISC-V Baseband System-on-Chip for Multi-Standard Integrated Sensing and Communications. - Limin Jiang; Yi Shi 004; Yihao Shen; Yintao Liu 001; Siyi Xu; Qingyu Deng; Xiaoxiao Chen; Qianli Wang; Shan Cao 001; Zhiyuan Jiang; Sheng Zhou 001 (DATE, 2026)

An Agile Systolic Array-Based Hardware Accelerator for Scalable Multi-Head Self-Attention. - Xinyu Chen 007; Yu Li 051; Beining Zhao 001; Yintao Liu 001; Shan Cao 001; Zhiyuan Jiang (IEEE Embed. Syst. Lett., 2026)

Venusian: Rapid Wireless Baseband Validation via High-Level Programming and FPGA-Based RISC-V Accelerator Co-Design. - Limin Jiang; Yi Shi 004; Yihao Shen; Yintao Liu 001; Shan Cao 001; Zhiyuan Jiang; Sheng Zhou 001 (IEEE Trans. Very Large Scale Integr. Syst., 2026)