Chiplet actuary: a quantitative cost model and multi-chiplet architecture exploration. - Yinxiao Feng; Kaisheng Ma (DAC, 2022)

A Scalable Methodology for Designing Efficient Interconnection Network of Chiplets. - Yinxiao Feng; Dong Xiang; Kaisheng Ma (HPCA, 2023)

Heterogeneous Die-to-Die Interfaces: Enabling More Flexible Chiplet Interconnection Systems. - Yinxiao Feng; Dong Xiang; Kaisheng Ma (MICRO, 2023)

Ring Road: A Scalable Polar-Coordinate-based 2D Network-on-Chip Architecture. - Yinxiao Feng; Wei Li; Kaisheng Ma (MICRO, 2024)

Switch-Less Dragonfly on Wafers: A Scalable Interconnection Architecture based on Wafer-Scale Integration. - Yinxiao Feng; Kaisheng Ma (SC, 2024)

Evaluating Chiplet-based Large-Scale Interconnection Networks via Cycle-Accurate Packet-Parallel Simulation. - Yinxiao Feng; Yuchen Wei; Dong Xiang; Kaisheng Ma (USENIX ATC, 2024)

RailX: A Flexible, Scalable, and Low-Cost Network Architecture for Hyper-Scale LLM Training Systems. - Yinxiao Feng; Tiancheng Chen; Yuchen Wei; Siyuan Shen; Shiju Wang; Wei Li; Kaisheng Ma; Torsten Hoefler (CoRR, 2025)