Characterization of Ge2Sb2Te5 thin film transistor and its application in non-volatile memory. - Feifei Liao; Yiqing Ding; Yinyin Lin; Tingao Tang; Baowei Qiao; Yunfeng Lai; Jie Feng; Bomy Chen (Microelectron. J., 2006)

Electronic properties of GST for non-volatile memory. - Hangbing Lv; Peng Zhou; Yinyin Lin; Tingao Tang; Baowei Qiao; Yunfeng Lai; Jie Feng; Bingchu Cai; Bomy Chen (Microelectron. J., 2006)

Multilevel Storage in Phase-Change Memory. - Yang Hong; Yinyin Lin; Tingao Tang; Bomy Chen (IEICE Trans. Electron., 2007)

A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell. - Ji Zhang 001; Yiqing Ding; Xiaoyong Xue; Gang Jin; Yuxin Wu; Yufeng Xie; Yinyin Lin (IEICE Trans. Electron., 2010)

Novel RRAM programming technology for instant-on and high-security FPGAs. - Xiaoyong Xue; Wenxiang Jian; Yufeng Xie; Qing Dong; Rui Yuan; Yinyin Lin (ASICON, 2011)

A BIST scheme for high-speed Gain Cell eDRAM. - Bing Yan; Yufeng Xie; Rui Yuan; Yinyin Lin (ASICON, 2011)

Novel 2T programmable element to improve density and performance of FPGA. - Xiaoyong Xue; Yufeng Xie; Yinyin Lin (IEICE Electron. Express, 2011)

A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction. - Xiaoyong Xue; W. X. Jian; Jianguo Yang; F. J. Xiao; G. Chen; X. L. Xu; Y. F. Xie; Yinyin Lin; R. Huang; Q. T. Zhou; J. G. Wu (VLSIC, 2012)

Variation-tolerant CuxSiyO-based RRAM for low power application. - Wenxiang Jian; Gang Jin; Na Yan; Zhongyu Bi; Hao Min; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (IEICE Electron. Express, 2012)

64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage. - Yufeng Xie; Wenxiang Jian; Xiaoyong Xue; Gang Jin; Yinyin Lin (IEICE Electron. Express, 2012)

Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM. - Hui Li; Wei Zhu; Ningxi Liu; Cunlin Dong; Chao Meng; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (ASICON, 2013)

Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing. - Ningxi Liu; Yu Jiang; Qing Dong; Hui Li; Xinyi Hu; Yinyin Lin (ASICON, 2013)

A 2Mb ReRAM with two bits error correction codes circuit for high reliability application. - Jianguo Yang; Ying Meng; Xiaoyong Xue; Ryan Huang; Q. T. Zhou; J. G. Wu; Yinyin Lin (ASICON, 2013)

A 0.13 µm 8 Mb Logic-Based Cux Siy O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction. - Xiaoyong Xue; Wenxiang Jian; Jianguo Yang; Fanjie Xiao; Gang Chen; Shuliu Xu; Yufeng Xie; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (IEEE J. Solid State Circuits, 2013)

A low cost and high reliability true random number generator based on resistive random access memory. - Jianguo Yang; Juan Xu; Bo Wang; Xiaoyong Xue; Ryan Huang; Qingtian Zou; Jingang Wu; Yinyin Lin (ASICON, 2015)

Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform. - Kai Yang; Yanqing Zhao; Jianguo Yang; Xiaoyong Xue; Yinyin Lin; Jun-Soo Bae (ASICON, 2015)

3D vertical RRAM architecture and operation algorithms with effective IR-drop suppressing and anti-disturbance. - Yinyin Lin; Rui Yuan; Xiaoyong Xue; B. A. Chen (ISCAS, 2015)

A compact pico-second in-situ sensor using programmable ring oscillators for advanced on chip variation characterization in 28nm HKMG. - Yinyin Lin; Xinyi Hu; Jianguo Yang; Xiaoyong Xue (ISCAS, 2016)

Novel 3D horizontal RRAM architecture with isolation cell structure for sneak current depression. - Yanqing Zhao; Juan Xu; Jianguo Yang; Xiaoyong Xue; Yinyin Lin; Jaehwang Sim (ISCAS, 2016)

A self-adaptive write driver with fast termination of step-up pulse for ReRAM. - Jianguo Yang; Xiaoyong Xue; Juan Xu; Fan Ye 001; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (IEICE Electron. Express, 2016)

A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security. - Yufeng Xie; Xiaoyong Xue; Jianguo Yang; Yinyin Lin; Qingtian Zou; Ryan Huang; Jingang Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Low-Power Variation-Tolerant Nonvolatile Lookup Table Design. - Xiaoyong Xue; Jianguo Yang; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations. - Yun Yin; Junlin Gou; Junyi Wang; Yarong Fu; Xiaoyong Xue; Yinyin Lin (ASICON, 2017)

A small area and low power true random number generator using write speed variation of oxidebased RRAM for IoT security application. - Jianguo Yang; Yinyin Lin; Yarong Fu; Xiaoyong Xue; B. A. Chen (ISCAS, 2017)

3D domain wall memory-cell structure, array architecture and operation algorithm with anti-disturbance. - Yarong Fu; Kai Yang; B. A. Chen; Yinyin Lin (Microelectron. J., 2017)

Retention-Aware Hybrid Main Memory (RAHMM): Big DRAM and Little SCM. - Weiliang Jing; Kai Yang; Yinyin Lin; Beomseop Lee; Sangkyu Yoon; Yong Ye; Yuan Du; Bomy Chen (IEEE Trans. Computers, 2017)

Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory. - Xiaoyong Xue; Yarong Fu; Yanqing Zhao; Juan Xu; Jianguo Yang; Yufeng Xie; Yinyin Lin; Ryan Huang; Qingtian Zou; Jingang Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Statistical Observations of Three Co-Existing NBTI Behaviors in 28 nm HKMG by On-Chip Monitor With Less Recovery Impact. - Yarong Fu; Wang Wang; Xin Zhong; Manni Li; Zixu Li; Qing Dong; Yu Jiang; Yinyin Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

ANS: Assimilating Near Similarity at High Accuracy for Significant Deduction of CNN Storage and Computation. - Wang Wang; Xin Zhong; Manni Li; Zixu Li; Yinyin Lin (IEEE Access, 2023)

LauWS: Local Adaptive Unstructured Weight Sparsity of Load Balance for DNN in Near-Data Processing. - Zixu Li; Wang Wang; Xin Zhong; Manni Li; Jiayu Yang; Yinyin Lin; Guhyun Kim; Yosub Song; Chengchen Wang; Xiankui Xiong (ISCAS, 2024)

Linearization of Quadrature Digital Power Amplifiers by Neural Network of ULR_LSTM: Unsupervised Learning Residual LSTM. - Jiayu Yang; Luyi Guo; Yicheng Li 002; Wang Wang; Zixu Li; Manni Li; Zijian Huang 017; Yinyin Lin; Yun Yin; Hongtao Xu (DATE, 2025)

Digital Predistortion for Quadrature Digital Power Amplifiers Using Deep Neural Network of AT_LSTM: Attention LSTM. - Jiayu Yang; Wending Zhao; Yicheng Li 002; Wang Wang; Zixu Li; Manni Li; Zijian Huang 017; Yinyin Lin; Yun Yin; Hongtao Xu (ACM Great Lakes Symposium on VLSI, 2025)

CPSnB: Compressing and Processing Spatial Similarity near Memory Bank for DNNs. - Wang Wang; Xin Zhong; Manni Li; Zixu Li; Jiayu Yang; Zijian Huang 017; Yinyin Lin; Chengchen Wang; Xiankui Xiong (ISCAS, 2025)

APCPU: Adaptive-Pooling Compression Processing Unit for Energy-Efficient DNNs Processing. - Wang Wang; Wending Zhao; Manni Li; Zixu Li; Jiayu Yang; Zijian Huang 017; Yinyin Lin; Chengchen Wang; Xiankui Xiong (ISCAS, 2025)

A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications. - Shuming Guo; Yinyin Lin; Hao Wang; Yao Li 018; Chongyan Gu; Weiqiang Liu 001; Yijun Cui (IEEE Trans. Very Large Scale Integr. Syst., 2025)