DFT guidance through RTL test justification and propagation analysis. - Yiorgos Makris; Alex Orailoglu (ITC, 1998)

RTL Test Justification and Propagation Analysis for Modular Designs. - Yiorgos Makris; Alex Orailoglu (J. Electron. Test., 1998)

TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generation. - Yiorgos Makris; Jamison Collins; Alex Orailoglu; Praveen Vishakantaiah (CICC, 1999)

Channel-Based Behavioral Test Synthesis for Improved Module Reachability. - Yiorgos Makris; Alex Orailoglu (DATE, 1999)

A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths. - Yiorgos Makris; Alex Orailoglu (DFT, 1999)

Property-based testability analysis for hierarchical RTL designs. - Yiorgos Makris; Alex Orailoglu (ICECS, 1999)

Fast hierarchical test path construction for DFT-free controller-datapath circuits. - Yiorgos Makris; Jamison Collins; Alex Orailoglu (Asian Test Symposium, 2000)

Modular test generation and concurrent transparency-based test translation using gate-level ATPG. - Yiorgos Makris; Alex Orailoglu; Praveen Vishakantaiah (CICC, 2000)

How to avoid random walks in hierarchical test path identification. - Yiorgos Makris; Jamison Collins; Alex Orailoglu (ETW, 2000)

Transparency-based hierarchical test generation for modular RTL designs. - Yiorgos Makris; Jamison Collins; Alex Orailoglu; Praveen Vishakantaiah (ISCAS, 2000)

Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line Test. - Yiorgos Makris; Alex Orailoglu (LATW, 2000)

Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. - Yiorgos Makris; Ismet Bayraktaroglu; Alex Orailoglu (VTS, 2000)

Efficient Transparency Extraction and Utilization in Hierarchical Test. - Yiorgos Makris; Vishal Patel; Alex Orailoglu (VTS, 2001)

Non-Intrusive Design of Concurrently Self-Testable FSMs. - Petros Drineas; Yiorgos Makris (Asian Test Symposium, 2002)

Test Requirement Analysis for Low Cost Hierarchical Test Path Construction. - Yiorgos Makris; Alex Orailoglu (Asian Test Symposium, 2002)

Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies. - Thomas Verdel; Yiorgos Makris (DFT, 2002)

Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface. - Yiorgos Makris; Jamison Collins; Alex Orailoglu (J. Electron. Test., 2002)

Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees. - Petros Drineas; Yiorgos Makris (DATE, 2003)

Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code. - Sobeeh Almukhaizim; Yiorgos Makris (DFT, 2003)

Low Cost Convolutional Code Based Concurrent Error Detection in FSMs. - Konstantinos Rokas; Yiorgos Makris; Dimitris Gizopoulos (DFT, 2003)

Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case. - Sobeeh Almukhaizim; Thomas Verdel; Yiorgos Makris (ICCD, 2003)

Independent Test Sequence Compaction through Integer Programming. - Petros Drineas; Yiorgos Makris (ICCD, 2003)

On Compaction-Based Concurrent Error Detection. - Sobeeh Almukhaizim; Petros Drineas; Yiorgos Makris (IOLTS, 2003)

Concurrent Fault Detection in Random Combinational Logic. - Petros Drineas; Yiorgos Makris (ISQED, 2003)

Concurrent Error Detection in Linear Analog Circuits Using State Estimation. - Haralampos-G. D. Stratigopoulos; Yiorgos Makris (ITC, 2003)

An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits. - Haralampos-G. D. Stratigopoulos; Yiorgos Makris (VTS, 2003)

SPaRe: selective partial replication for concurrent fault-detection in FSMs. - Petros Drineas; Yiorgos Makris (IEEE Trans. Instrum. Meas., 2003)

On Concurrent Error Detection with Bounded Latency in FSMs. - Sobeeh Almukhaizim; Petros Drineas; Yiorgos Makris (DATE, 2004)

Fault simulation and random test generation for speed-independent circuits. - Feng Shi 010; Yiorgos Makris (ACM Great Lakes Symposium on VLSI, 2004)

SPIN-TEST: automatic test pattern generation for speed-independent circuits. - Feng Shi 010; Yiorgos Makris (ICCAD, 2004)

Compiler-Based Frame Formation for Static Optimization. - Feng Shi 010; Sobeeh Almukhaizim; Pey-Chang Lin; Yiorgos Makris (ICCD, 2004)

Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction. - Sobeeh Almukhaizim; Petros Drineas; Yiorgos Makris (ISQED, 2004)

SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits. - Feng Shi 010; Yiorgos Makris (ITC, 2004)

Cost-Driven Selection of Parity Trees. - Sobeeh Almukhaizim; Petros Drineas; Yiorgos Makris (VTS, 2004)

An Analog Checker with Input-Relative Tolerance for Duplicate Signals. - Haralampos-G. D. Stratigopoulos; Yiorgos Makris (J. Electron. Test., 2004)

Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test. - Yiorgos Makris; Ismet Bayraktaroglu; Alex Orailoglu (IEEE Trans. Reliab., 2004)

SPIN-PAC: test compaction for speed-independent circuits. - Feng Shi 010; Yiorgos Makris (ASP-DAC, 2005)

Concurrent Error Detection in Asynchronous Burst-Mode Controllers. - Sobeeh Almukhaizim; Yiorgos Makris (DATE, 2005)

Generating decision regions in analog measurement spaces. - Haralampos-G. D. Stratigopoulos; Yiorgos Makris (ACM Great Lakes Symposium on VLSI, 2005)

Test generation for ultra-high-speed asynchronous pipelines. - Feng Shi 010; Yiorgos Makris; Steven M. Nowick; Montek Singh (ITC, 2005)

Constructive Derivation of Analog Specification Test Criteria. - Haralampos-G. D. Stratigopoulos; Yiorgos Makris (VTS, 2005)

Compaction-based concurrent error detection for digital circuits. - Sobeeh Almukhaizim; Petros Drineas; Yiorgos Makris (Microelectron. J., 2005)

Nonlinear decision boundaries for testing analog circuits. - Haralampos-G. D. Stratigopoulos; Yiorgos Makris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines. - Gennette Gill; Ankur Agiwal; Montek Singh; Feng Shi 010; Yiorgos Makris (ASYNC, 2006)

A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines. - Feng Shi 010; Yiorgos Makris (ASYNC, 2006)

Berger code-based concurrent error detection in asynchronous burst-mode machines. - Sobeeh Almukhaizim; Yiorgos Makris (DATE, 2006)

Testing delay faults in asynchronous handshake circuits. - Feng Shi 010; Yiorgos Makris (ICCAD, 2006)

Seamless Integration of SER in Rewiring-Based Design Space Exploration. - Sobeeh Almukhaizim; Yiorgos Makris; Yu-Shen Yang; Andreas G. Veneris (ITC, 2006)

Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing. - Haralampos-G. D. Stratigopoulos; Yiorgos Makris (VTS, 2006)

Session Abstract. - Andreas G. Veneris; Yiorgos Makris (VTS, 2006)

An adaptive checker for the fully differential analog code. - Haralampos-G. D. Stratigopoulos; Yiorgos Makris (IEEE J. Solid State Circuits, 2006)

Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines. - Sobeeh Almukhaizim; Petros Drineas; Yiorgos Makris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Concurrent detection of erroneous responses in linear analog circuits. - Haralampos-G. D. Stratigopoulos; Yiorgos Makris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Non-RF to RF Test Correlation Using Learning Machines: A Case Study. - Haralampos-G. D. Stratigopoulos; Petros Drineas; Mustapha Slamani; Yiorgos Makris (VTS, 2007)

On the identification of modular test requirements for low cost hierarchical test path construction. - Yiorgos Makris; Alex Orailoglu (Integr., 2007)

Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines. - Sobeeh Almukhaizim; Yiorgos Makris (IEEE Trans. Computers, 2007)

Coping with Soft Errors in Asynchronous Burst-Mode Machines. - Sobeeh Almukhaizim; Feng Shi 010; Yiorgos Makris (ASYNC, 2008)

Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller. - Michail Maniatakos; Naghmeh Karimi; Yiorgos Makris; Abhijit Jas; Chandra Tirumurti (DFT, 2008)

Confidence Estimation in Non-RF to RF Correlation-Based Specification Test Compaction. - Nathan Kupp; Petros Drineas; Mustapha Slamani; Yiorgos Makris (ETS, 2008)

Hardware Trojan Detection Using Path Delay Fingerprint. - Yier Jin; Yiorgos Makris (HOST, 2008)

On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. - Sobeeh Almukhaizim; Yiorgos Makris; Yu-Shen Yang; Andreas G. Veneris (IOLTS, 2008)

On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors. - Naghmeh Karimi; Michail Maniatakos; Abhijit Jas; Yiorgos Makris (ITC, 2008)

A Statistical Approach to Characterizing and Testing Functionalized Nanowires. - James Dardig; Haralampos-G. D. Stratigopoulos; Eric Stern; Mark A. Reed; Yiorgos Makris (VTS, 2008)

Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing. - Haralampos-G. D. Stratigopoulos; Yiorgos Makris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires. - Sobeeh Almukhaizim; Yiorgos Makris (IEEE Trans. Reliab., 2008)

Enrichment of limited training sets in machine-learning-based analog/RF test. - Haralampos-G. D. Stratigopoulos; Salvador Mir; Yiorgos Makris (DATE, 2009)

Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors. - Yiorgos Makris (DFT, 2009)

Experiences in Hardware Trojan Design and Implementation. - Yier Jin; Nathan Kupp; Yiorgos Makris (HOST, 2009)

Impact analysis of performance faults in modern microprocessors. - Naghmeh Karimi; Michail Maniatakos; Chandra Tirumurti; Abhijit Jas; Yiorgos Makris (ICCD, 2009)

Special Session 7C: TTTC 2009 Best Doctoral Thesis Contest. - Yiorgos Makris; Haralampos-G. D. Stratigopoulos (VTS, 2009)

Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller. - Michail Maniatakos; Naghmeh Karimi; Chandra Tirumurti; Abhijit Jas; Yiorgos Makris (VTS, 2009)

On Boosting the Accuracy of Non-RF to RF Correlation-Based Specification Test Compaction. - Nathan Kupp; Petros Drineas; Mustapha Slamani; Yiorgos Makris (J. Electron. Test., 2009)

Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits. - Feng Shi 010; Yiorgos Makris (IEEE Trans. Computers, 2009)

Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits. - Sobeeh Almukhaizim; Feng Shi 010; Eric Love; Yiorgos Makris (IEEE Trans. Very Large Scale Integr. Syst., 2009)

DFTT: Design for Trojan Test. - Yier Jin; Nathan Kupp; Yiorgos Makris (ICECS, 2010)

An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits. - Dzmitry Maliuk; Haralampos-G. D. Stratigopoulos; Yiorgos Makris (IOLTS, 2010)

Post-production performance calibration in analog/RF devices. - Nathan Kupp; He Huang; Petros Drineas; Yiorgos Makris (ITC, 2010)

Analog neural network design for RF built-in self-test. - Dzmitry Maliuk; Haralampos-G. D. Stratigopoulos; He Huang; Yiorgos Makris (ITC, 2010)

Workload-driven selective hardening of control state elements in modern microprocessors. - Michail Maniatakos; Yiorgos Makris (VTS, 2010)

Hardware Trojans in Wireless Cryptographic ICs. - Yier Jin; Yiorgos Makris (IEEE Des. Test Comput., 2010)

RF Specification Test Compaction Using Learning Machines. - Haralampos-G. D. Stratigopoulos; Petros Drineas; Mustapha Slamani; Yiorgos Makris (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Correlating inline data with final test outcomes in analog/RF devices. - Nathan Kupp; Mustapha Slamani; Yiorgos Makris (DATE, 2011)

AVF Analysis Acceleration via Hierarchical Fault Pruning. - Michail Maniatakos; Chandra Tirumurti; Abhijit Jas; Yiorgos Makris (ETS, 2011)

Enhancing security via provably trustworthy hardware intellectual property. - Eric Love; Yier Jin; Yiorgos Makris (HOST, 2011)

On proving the efficiency of alternative RF tests. - Nathan Kupp; Haralampos-G. D. Stratigopoulos; Petros Drineas; Yiorgos Makris (ICCAD, 2011)

Is single-scheme Trojan prevention sufficient? - Yier Jin; Yiorgos Makris (ICCD, 2011)

PSCML: Pseudo-Static Current Mode Logic. - Yier Jin; Yiorgos Makris (ICECS, 2011)

Exponent monitoring for low-cost concurrent error detection in FPU control logic. - Michail Maniatakos; Yiorgos Makris; Prabhakar Kudva; Bruce M. Fleischer (VTS, 2011)

Improving Analog and RF Device Yield through Performance Calibration. - Nathan Kupp; He Huang; Yiorgos Makris; Petros Drineas (IEEE Des. Test Comput., 2011)

Guest Editors' Introduction: Special Section on Chips and Architectures for Emerging Technologies and Applications. - Alfredo Benso; Yiorgos Makris; Pinaki Mazumder (IEEE Trans. Computers, 2011)

Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor. - Naghmeh Karimi; Michail Maniatakos; Abhijit Jas; Chandra Tirumurti; Yiorgos Makris (IEEE Trans. Computers, 2011)

Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller. - Michail Maniatakos; Naghmeh Karimi; Chandra Tirumurti; Abhijit Jas; Yiorgos Makris (IEEE Trans. Computers, 2011)

Post-deployment trust evaluation in wireless cryptographic ICs. - Yier Jin; Dzmitry Maliuk; Yiorgos Makris (DATE, 2012)

Parametric counterfeit IC detection via Support Vector Machines. - Ke Huang 001; John M. Carulli Jr.; Yiorgos Makris (DFT, 2012)

Spatial correlation modeling for probe test cost reduction in RF devices. - Nathan Kupp; Ke Huang 001; John M. Carulli Jr.; Yiorgos Makris (ICCAD, 2012)

Exposing vulnerabilities of untrusted computing platforms. - Yier Jin; Michail Maniatakos; Yiorgos Makris (ICCD, 2012)

A dual-mode weight storage analog neural network platform for on-chip applications. - Dzmitry Maliuk; Yiorgos Makris (ISCAS, 2012)

Spatial estimation of wafer measurement parameters using Gaussian process models. - Nathan Kupp; Ke Huang 001; John M. Carulli Jr.; Yiorgos Makris (ITC, 2012)

Integrated optimization of semiconductor manufacturing: A machine learning approach. - Nathan Kupp; Yiorgos Makris (ITC, 2012)

Vulnerability-based Interleaving for Multi-Bit Upset (MBU) protection in modern microprocessors. - Michail Maniatakos; Maria K. Michael; Yiorgos Makris (ITC, 2012)

Proof carrying-based information flow tracking for data secrecy protection and hardware trust. - Yier Jin; Yiorgos Makris (VTS, 2012)

Towards a fully stand-alone analog/RF BIST: A cost-effective implementation of a neural classifier. - Dzmitry Maliuk; Nathan Kupp; Yiorgos Makris (VTS, 2012)

Applying the Model-View-Controller Paradigm to Adaptive Test. - Nathan Kupp; Yiorgos Makris (IEEE Des. Test Comput., 2012)

Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors. - Michail Maniatakos; Chandrasekharan Tirumurti; Rajesh Galivanche; Yiorgos Makris (IEEE Trans. Computers, 2012)

Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition. - Eric Love; Yier Jin; Yiorgos Makris (IEEE Trans. Inf. Forensics Secur., 2012)

Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests. - Ke Huang 001; Nathan Kupp; John M. Carulli Jr.; Yiorgos Makris (DATE, 2013)

AVF-driven parity optimization for MBU protection of in-core memory arrays. - Michail Maniatakos; Maria K. Michael; Yiorgos Makris (DATE, 2013)

On combining alternate test with spatial correlation modeling in analog/RF ICs. - Ke Huang 001; Nathan Kupp; John M. Carulli Jr.; Yiorgos Makris (ETS, 2013)

Reconciling the IC test and security dichotomy. - Ozgur Sinanoglu; Naghmeh Karimi; Jeyavijayan Rajendran; Ramesh Karri; Yier Jin; Ke Huang 001; Yiorgos Makris (ETS, 2013)

Cycle-accurate information assurance by proof-carrying based signal sensitivity tracing. - Yier Jin; Bo Yang; Yiorgos Makris (HOST, 2013)

A proof-carrying based framework for trusted microprocessor IP. - Yier Jin; Yiorgos Makris (ICCAD, 2013)

Hardware Trojans in wireless cryptographic ICs: silicon demonstration & detection method evaluation. - Yu Liu; Yier Jin; Yiorgos Makris (ICCAD, 2013)

A post-deployment IC trust evaluation architecture. - Yier Jin; Dzmitry Maliuk; Yiorgos Makris (IOLTS, 2013)

Investigating the limits of AVF analysis in the presence of multiple bit errors. - Michail Maniatakos; Maria K. Michael; Yiorgos Makris (IOLTS, 2013)

Counterfeit electronics: A rising threat in the semiconductor manufacturing industry. - Ke Huang 001; John M. Carulli; Yiorgos Makris (ITC, 2013)

Process monitoring through wafer-level spatial variation decomposition. - Ke Huang 001; Nathan Kupp; John M. Carulli Jr.; Yiorgos Makris (ITC, 2013)

Innovative practices session 7C: Self-calibration & trimming. - Chen-Yong Cher; Yiorgos Makris; C. Thibeault; Alan J. Drake (VTS, 2013)

On the Impact of Performance Faults in Modern Microprocessors. - Naghmeh Karimi; Michail Maniatakos; Chandrasekharan Tirumurti; Yiorgos Makris (J. Electron. Test., 2013)

Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers. - Michail Maniatakos; Prabhakar Kudva; Bruce M. Fleischer; Yiorgos Makris (IEEE Trans. Computers, 2013)

Hardware Trojan Detection through Golden Chip-Free Statistical Side-Channel Fingerprinting. - Yu Liu; Ke Huang 001; Yiorgos Makris (DAC, 2014)

An analog non-volatile neural network platform for prototyping RF BIST solutions. - Dzmitry Maliuk; Yiorgos Makris (DATE, 2014)

Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation. - Ali Ahmadi; Ke Huang 001; Suriyaprakash Natarajan; John M. Carulli Jr.; Yiorgos Makris (ITC, 2014)

IC laser trimming speed-up through wafer-level spatial correlation modeling. - Constantinos Xanthopoulos; Ke Huang 001; Abbas Poonawala; Amit Nahar; Bob Orr; John M. Carulli Jr.; Yiorgos Makris (ITC, 2014)

On-chip intelligence: A pathway to self-testable, tunable, and trusted analog/RF ICs. - Dzmitry Maliuk; Yiorgos Makris (MWSCAS, 2014)

Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain. - Ujjwal Guin; Ke Huang 001; Daniel DiMase; John M. Carulli; Mohammad Tehranipoor; Yiorgos Makris (Proc. IEEE, 2014)

Toward automatic proof generation for information flow policies in third-party hardware IP. - Mohammad-Mahdi Bidmeshki; Yiorgos Makris (HOST, 2015)

Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion. - Ali Ahmadi; Haralampos-G. D. Stratigopoulos; Amit Nahar; Bob Orr; Michael Pas; Yiorgos Makris (ICCAD, 2015)

Workload characterization and prediction: A pathway to reliable multi-core systems. - Monir Zaman; Ali Ahmadi; Yiorgos Makris (IOLTS, 2015)

VeriCoq: A Verilog-to-Coq converter for proof-carrying hardware automation. - Mohammad-Mahdi Bidmeshki; Yiorgos Makris (ISCAS, 2015)

Silicon Demonstration of Statistical Post-Production Tuning. - Yichuan Lu; Kiruba S. Subramani; He Huang; Nathan Kupp; Yiorgos Makris (ISVLSI, 2015)

Concurrent hardware Trojan detection in wireless cryptographic ICs. - Yu Liu; Georgios Volanis; Ke Huang 001; Yiorgos Makris (ITC, 2015)

A comparative study of one-shot statistical calibration methods for analog / RF ICs. - Yichuan Lu; Kiruba S. Subramani; He Huang; Nathan Kupp; Ke Huang 001; Yiorgos Makris (ITC, 2015)

Yield prognosis for fab-to-fab product migration. - Ali Ahmadi; Ke Huang 001; Amit Nahar; Bob Orr; Michael Pas; John M. Carulli; Yiorgos Makris (VTS, 2015)

Low-Cost Analog/RF IC Testing Through Combined Intra- and Inter-Die Correlation Models. - Ke Huang 001; Nathan Kupp; Constantinos Xanthopoulos; John M. Carulli Jr.; Yiorgos Makris (IEEE Des. Test, 2015)

Revisiting Vulnerability Analysis in Modern Microprocessors. - Michail Maniatakos; Maria K. Michael; Chandra Tirumurti; Yiorgos Makris (IEEE Trans. Computers, 2015)

Recycled IC Detection Based on Statistical Methods. - Ke Huang 001; Yu Liu; Nenad Korolija; John M. Carulli; Yiorgos Makris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Guest Editorial Special Section on Hardware Security and Trust. - Ramesh Karri; Farinaz Koushanfar; Ozgur Sinanoglu; Yiorgos Makris; Ken Mai; Ahmad-Reza Sadeghi; Swarup Bhunia (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

An Experimentation Platform for On-Chip Integration of Analog Neural Networks: A Pathway to Trusted and Robust Analog/RF ICs. - Dzmitry Maliuk; Yiorgos Makris (IEEE Trans. Neural Networks Learn. Syst., 2015)

Multiple-Bit Upset Protection in Microprocessor Memory Arrays Using Vulnerability-Based Parity Optimization and Interleaving. - Michail Maniatakos; Maria K. Michael; Yiorgos Makris (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Hardware-based workload forensics: Process reconstruction via TLB monitoring. - Liwei Zhou; Yiorgos Makris (HOST, 2016)

A machine learning approach to fab-of-origin attestation. - Ali Ahmadi; Mohammad-Mahdi Bidmeshki; Amit Nahar; Bob Orr; Michael Pas; Yiorgos Makris (ICCAD, 2016)

Hardware-based attacks to compromise the cryptographic security of an election system. - Mohammad-Mahdi Bidmeshki; Gaurav Rajavendra Reddy; Liwei Zhou; Jeyavijayan Rajendran; Yiorgos Makris (ICCD, 2016)

Harnessing fabrication process signature for predicting yield across designs. - Ali Ahmadi; Haralampos-G. D. Stratigopoulos; Amit Nahar; Bob Orr; Michael Pas; Yiorgos Makris (ISCAS, 2016)

Harnessing process variations for optimizing wafer-level probe-test flow. - Ali Ahmadi; Constantinos Xanthopoulos; Amit Nahar; Bob Orr; Michael Pas; Yiorgos Makris (ITC, 2016)

Hardware-Based Workload Forensics and Malware Detection in Microprocessors. - Liwei Zhou; Yiorgos Makris (MTV, 2016)

-197dBc/Hz FOM 4.3-GHz VCO Using an addressable array of minimum-sized nmos cross-coupled transistor pairs in 65-nm CMOS. - Amit Jha; Ali Ahmadi; Sandeep Kshattry; T. Cao; K. Liao; Geoffrey Yeap; Yiorgos Makris; Kenneth K. O (VLSI Circuits, 2016)

Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs. - Ali Ahmadi; Amit Nahar; Bob Orr; Michael Pas; Yiorgos Makris (VTS, 2016)

On-die learning-based self-calibration of analog/RF ICs. - Georgios Volanis; Dzmitry Maliuk; Yichuan Lu; Kiruba S. Subramani; Angelos Antonopoulos 002; Yiorgos Makris (VTS, 2016)

Toward Silicon-Based Cognitive Neuromorphic ICs - A Survey. - Georgios Volanis; Angelos Antonopoulos 002; Alkis A. Hatzopoulos; Yiorgos Makris (IEEE Des. Test, 2016)

Information flow tracking in analog/mixed-signal designs through proof-carrying hardware IP. - Mohammad-Mahdi Bidmeshki; Angelos Antonopoulos 002; Yiorgos Makris (DATE, 2017)

A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration. - Jingxiang Tian; Gaurav Rajavendra Reddy; Jiajia Wang; William Swartz; Yiorgos Makris; Carl Sechen (DATE, 2017)

Hardware-based on-line intrusion detection via system call routine fingerprinting. - Liwei Zhou; Yiorgos Makris (DATE, 2017)

Security and trust in the analog/mixed-signal/RF domain: A survey and a perspective. - Angelos Antonopoulos 002; Christiana Kapatsori; Yiorgos Makris (ETS, 2017)

What to Lock?: Functional and Parametric Locking. - Muhammad Yasin; Abhrajit Sengupta; Benjamin Carrión Schäfer; Yiorgos Makris; Ozgur Sinanoglu; Jeyavijayan Rajendran (ACM Great Lakes Symposium on VLSI, 2017)

INFECT: INconspicuous FEC-based Trojan: A hardware attack on an 802.11a/g wireless network. - Kiruba Sankaran Subramani; Angelos Antonopoulos 002; Ahmed Attia Abotabl; Aria Nosratinia; Yiorgos Makris (HOST, 2017)

ACE: Adaptive channel estimation for detecting analog/RF trojans in WLAN transceivers. - Kiruba Sankaran Subramani; Angelos Antonopoulos 002; Ahmed Attia Abotabl; Aria Nosratinia; Yiorgos Makris (ICCAD, 2017)

Wafer-level adaptive trim seed forecasting based on E-tests. - Constantinos Xanthopoulos; Ali Ahmadi; Sirish Boddikurapati; Amit Nahar; Bob Orr; Yiorgos Makris (ISCAS, 2017)

Automated die inking: A pattern recognition-based approach. - Constantinos Xanthopoulos; Peter Sarson; Heinz Reiter; Yiorgos Makris (ITC, 2017)

Knob non-idealities in learning-based post-production tuning of analog/RF ICs: Impact & remedies. - Yichuan Lu; Georgios Volanis; Kiruba S. Subramani; Angelos Antonopoulos 002; Yiorgos Makris (VTS, 2017)

Foreword. - Yiorgos Makris; Srivaths Ravi 001; Amit Majumdar 002 (VTS, 2017)

Trusted Analog/Mixed- Signal/RF ICs: A Survey and a Perspective. - Angelos Antonopoulos 002; Christiana Kapatsori; Yiorgos Makris (IEEE Des. Test, 2017)

Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations. - Ali Ahmadi; Haralampos-G. D. Stratigopoulos; Ke Huang 001; Amit Nahar; Bob Orr; Michael Pas; John M. Carulli; Yiorgos Makris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part II: Framework Automation. - Mohammad-Mahdi Bidmeshki; Xiaolong Guo; Raj Gautam Dutta; Yier Jin; Yiorgos Makris (IEEE Trans. Inf. Forensics Secur., 2017)

Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part I: Framework Fundamentals. - Yier Jin; Xiaolong Guo; Raj Gautam Dutta; Mohammad-Mahdi Bidmeshki; Yiorgos Makris (IEEE Trans. Inf. Forensics Secur., 2017)

Silicon Demonstration of Hardware Trojan Design and Detection in Wireless Cryptographic ICs. - Yu Liu; Yier Jin; Aria Nosratinia; Yiorgos Makris (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Towards provably-secure performance locking. - Monir Zaman; Abhrajit Sengupta; Danqing Liu; Ozgur Sinanoglu; Yiorgos Makris; Jeyavijayan (JV) Rajendran (DATE, 2018)

Hardware-assisted rootkit detection via on-line statistical fingerprinting of process execution. - Liwei Zhou; Yiorgos Makris (DATE, 2018)

On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs. - Martin Andraud; Laura Isabel Galindez Olascoaga; Yichuan Lu; Yiorgos Makris; Marian Verhelst (ITC, 2018)

Hardware Dithering: A Run-Time Method for Trojan Neutralization in Wireless Cryptographic ICs. - Christiana Kapatsori; Yu Liu; Angelos Antonopoulos 002; Yiorgos Makris (ITC, 2018)

Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs. - Monir Zaman; Mustafa M. Shihab; Ayse K. Coskun; Yiorgos Makris (PATMOS, 2018)

Special session on machine learning: How will machine learning transform test? - Yiorgos Makris; Amit Nahar; Haralampos-G. D. Stratigopoulos; Marc Hutner (VTS, 2018)

Enhanced hotspot detection through synthetic pattern generation and design of experiments. - Gaurav Rajavendra Reddy; Constantinos Xanthopoulos; Yiorgos Makris (VTS, 2018)

Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. - Mustafa M. Shihab; Jingxiang Tian; Gaurav Rajavendra Reddy; Bo Hu; William Swartz; Benjamin Carrión Schäfer; Carl Sechen; Yiorgos Makris (DATE, 2019)

Wafer-Level Adaptive Vmin Calibration Seed Forecasting. - Constantinos Xanthopoulos; Deepika Neethirajan; Sirish Boddikurapati; Amit Nahar; Yiorgos Makris (DATE, 2019)

Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. - Bo Hu; Jingxiang Tian; Mustafa M. Shihab; Gaurav Rajavendra Reddy; William Swartz; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (ACM Great Lakes Symposium on VLSI, 2019)

Machine Learning-Based Hotspot Detection: Fallacies, Pitfalls and Marching Orders. - Gaurav Rajavendra Reddy; Kareem Madkour; Yiorgos Makris (ICCAD, 2019)

Revisiting Capacitor-Based Trojan Design. - Mohammad-Mahdi Bidmeshki; Kiruba Sankaran Subramani; Yiorgos Makris (ICCD, 2019)

Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage. - Bo Hu; Mustafa M. Shihab; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (FPT, 2019)

Trusted and Secure Design of Analog/RF ICs: Recent Developments. - Kiruba S. Subramani; Georgios Volanis; Mohammad-Mahdi Bidmeshki; Angelos Antonopoulos 002; Yiorgos Makris (IOLTS, 2019)

Automated Die Inking through On-line Machine Learning. - Constantinos Xanthopoulos; Arnold Neckermann; Paulus List; Klaus-Peter Tschernay; Peter Sarson; Yiorgos Makris (IOLTS, 2019)

Subtle Anomaly Detection of Microscopic Probes using Deep learning based Image Completion. - Kosuke Ikeda; Keith Schaub; Ira Leventhal; Yiorgos Makris; Constantinos Xanthopoulos; Deepika Neethirajan (ITC, 2019)

VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration. - Gaurav Rajavendra Reddy; Mohammad-Mahdi Bidmeshki; Yiorgos Makris (ITC, 2019)

Design Space Exploration for Hotspot Detection. - Gaurav Rajavendra Reddy; Yiorgos Makris (MTV, 2019)

Post-Production Calibration of Analog/RF ICs: Recent Developments and A Fully Integrated Solution. - Angelos Antonopoulos 002; Georgios Volanis; Yichuan Lu; Yiorgos Makris (SMACD, 2019)

Machine Learning-based Noise Classification and Decomposition in RF Transceivers. - Deepika Neethirajan; Constantinos Xanthopoulos; Kiruba S. Subramani; Keith Schaub; Ira Leventhal; Yiorgos Makris (VTS, 2019)

Analog Performance Locking through Neural Network-Based Biasing. - Georgios Volanis; Yichuan Lu; Sai Govinda Rao Nimmalapudi; Angelos Antonopoulos 002; Andrew Marshall; Yiorgos Makris (VTS, 2019)

Hardware-based Real-time Workload Forensics via Frame-level TLB Profiling. - Yunjie Zhang; Liwei Zhou; Yiorgos Makris (VTS, 2019)

CAPE: A cross-layer framework for accurate microprocessor power estimation. - Monir Zaman; Mustafa M. Shihab; Ayse K. Coskun; Yiorgos Makris (Integr., 2019)

Demonstrating and Mitigating the Risk of an FEC-Based Hardware Trojan in Wireless Networks. - Kiruba Sankaran Subramani; Angelos Antonopoulos 002; Ahmed Attia Abotabl; Aria Nosratinia; Yiorgos Makris (IEEE Trans. Inf. Forensics Secur., 2019)

Hardware-Based Detection of Spectre Attacks: A Machine Learning Approach. - Yunjie Zhang; Yiorgos Makris (AsianHOST, 2020)

DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY. - Jianqi Chen; Monir Zaman; Yiorgos Makris; R. D. Shawn Blanton; Subhasish Mitra; Benjamin Carrión Schäfer (DAC, 2020)

An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs. - Bo Hu; Mustafa M. Shihab; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (DATE, 2020)

Range-Controlled Floating-Gate Transistors: A Unified Solution for Unlocking and Calibrating Analog ICs. - Sai Govinda Rao Nimmalapudi; Georgios Volanis; Yichuan Lu; Angelos Antonopoulos 002; Andrew Marshall; Yiorgos Makris (DATE, 2020)

CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric. - Mustafa M. Shihab; Bharath Ramanidharan; Gaurav Rajavendra Reddy; Jingxiang Tian; William Swartz; Carl Sechen; Yiorgos Makris (ISCAS, 2020)

ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric. - Mustafa Munawar Shihab; Bharath Ramanidharan; Suraag Sunil Tellakula; Gaurav Rajavendra Reddy; Jingxiang Tian; Carl Sechen; Yiorgos Makris (VTS, 2020)

Hardware-Based Real-Time Workload Forensics. - Yunjie Zhang; Liwei Zhou; Yiorgos Makris (IEEE Des. Test, 2020)

A Hardware-Based Architecture-Neutral Framework for Real-Time IoT Workload Forensics. - Liwei Zhou; Yang Hu 001; Yiorgos Makris (IEEE Trans. Computers, 2020)

Amplitude-Modulating Analog/RF Hardware Trojans in Wireless Networks: Risks and Remedies. - Kiruba Sankaran Subramani; Noha M. Helal; Angelos Antonopoulos 002; Aria Nosratinia; Yiorgos Makris (IEEE Trans. Inf. Forensics Secur., 2020)

Secure Logic Locking with Strain-Protected Nanomagnet Logic. - Naimul Hassan; Alexander J. Edwards; Dhritiman Bhattacharya; Mustafa M. Shihab; Varun Venkat; Peng Zhou; Xuan Hu 002; Shamik Kundu; Abraham Peedikayil Kuruvila; Kanad Basu; Jayasimha Atulasimha; Yiorgos Makris; et al. (DAC, 2021)

Functional Locking through Omission: From HLS to Obfuscated Design. - Zi Wang 006; Shayan Omais Mohammed; Yiorgos Makris; Benjamin Carrión Schäfer (ICCD, 2021)

Trim Time Reduction in Analog/RF ICs Based on Inter-Trim Correlation. - V. A. Niranjan; Deepika Neethirajan; Constantinos Xanthopoulos; E. De La Rosa; C. Alleyne; S. Mier; Yiorgos Makris (VTS, 2021)

Improved Static Hand Gesture Classification on Deep Convolutional Neural Networks Using Novel Sterile Training Technique. - Josiah W. Smith; Shiva Thiagarajan; Richard Willis; Yiorgos Makris; Murat Torlak (IEEE Access, 2021)

Hunting Security Bugs in SoC Designs: Lessons Learned. - Mohammad-Mahdi Bidmeshki; Yunjie Zhang; Monir Zaman; Liwei Zhou; Yiorgos Makris (IEEE Des. Test, 2021)

Proof-Carrying Hardware-Based Information Flow Tracking in Analog/Mixed-Signal Designs. - Mohammad-Mahdi Bidmeshki; Angelos Antonopoulos 002; Yiorgos Makris (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

TPE: A Hardware-Based TLB Profiling Expert for Workload Reconstruction. - Liwei Zhou; Yunjie Zhang; Yiorgos Makris (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

Bias Busters: Robustifying DL-Based Lithographic Hotspot Detectors Against Backdooring Attacks. - Kang Liu 017; Benjamin Tan 001; Gaurav Rajavendra Reddy; Siddharth Garg; Yiorgos Makris; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

On Improving Hotspot Detection Through Synthetic Pattern-Based Database Enhancement. - Gaurav Rajavendra Reddy; Constantinos Xanthopoulos; Yiorgos Makris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A defect tolerance framework for improving yield. - Shiva Shankar Thiagarajan; Suriyaprakash Natarajan; Yiorgos Makris (DAC, 2022)

Physically and Algorithmically Secure Logic Locking with Hybrid CMOS/Nanomagnet Logic Circuits. - Alexander J. Edwards; Naimul Hassan; Dhritiman Bhattacharya; Mustafa M. Shihab; Peng Zhou; Xuan Hu 002; Jayasimha Atulasimha; Yiorgos Makris; Joseph S. Friedman (DATE, 2022)

Efficient CNN-Based Super Resolution Algorithms for Mmwave Mobile Radar Imaging. - Christos Vasileiou; Josiah W. Smith; Shiva Thiagarajan; Matthew Nigh; Yiorgos Makris; Murat Torlak (ICIP, 2022)

Machine Learning-Based Overkill Reduction through Inter-Test Correlation. - Deepika Neethirajan; V. A. Niranjan; Richard Willis; Amit Nahar; D. Webster; Yiorgos Makris (VTS, 2022)

Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric. - Apurva Jain; Thomas Broadfoot; Yiorgos Makris; Carl Sechen (DATE, 2023)

MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitS. - Chaitali Sathe; Yiorgos Makris; Benjamin Carrion Schafer (DATE, 2023)

FuncTeller: How Well Does eFPGA Hide Functionality? - Zhaokun Han; Mohammed Shayan; Aneesh Dixit; Mustafa M. Shihab; Yiorgos Makris; Jeyavijayan Rajendran (USENIX Security Symposium, 2023)

Machine Learning-Based Adaptive Outlier Detection for Underkill Reduction in Analog/RF IC Testing. - V. A. Niranjan; Deepika Neethirajan; Constantinos Xanthopoulos; D. Webster; Amit Nahar; Yiorgos Makris (VTS, 2023)

Unlocking Hardware Security Assurance: The Potential of LLMs. - Xingyu Meng; Amisha Srivastava; Ayush Arunachalam; Avik Ray; Pedro Henrique Silva; Rafail Psiakis; Yiorgos Makris; Kanad Basu (CoRR, 2023)

NSPG: Natural language Processing-based Security Property Generator for Hardware Security Assurance. - Xingyu Meng; Amisha Srivastava; Ayush Arunachalam; Avik Ray; Pedro Henrique Silva; Rafail Psiakis; Yiorgos Makris; Kanad Basu (DAC, 2024)

Generation and Quality Evaluation of Synthetic Process Control Monitoring Data. - Matthew Nigh; John M. Carulli; Yiorgos Makris (ITC, 2024)

On the Sensitivity of Analog Artificial Neural Network Models to Process Variation. - N. Afroz; A. Sayem; Georgios Volanis; Dzmitry Maliuk; Haralampos-G. Stratigopoulos; Yiorgos Makris (VTS, 2024)

Testing a Transistor-Level Programmable Fabric: Challenges and Solutions. - Apurva Jain; Thomas Broadfoot; Carl Sechen; Yiorgos Makris (VTS, 2024)

Statistical Methods for Detecting Recycled Electronics: From ICs to PCBs and Beyond. - Ke Huang 001; Yu Liu; Nenad Korolija; John M. Carulli; Yiorgos Makris (IEEE Des. Test, 2024)

Bit-by-Bit: Investigating the Vulnerabilities of Binary Neural Networks to Adversarial Bit Flipping. - Shamik Kundu; Sanjay Das; Sayar Karmakar; Arnab Raha; Souvik Kundu 009; Yiorgos Makris; Kanad Basu (Trans. Mach. Learn. Res., 2024)

Efficient and Secure Cloud-based Split Logic Synthesis. - Chaitali Sathe; Yiorgos Makris; Benjamin Carrión Schäfer (ASP-DAC, 2025)

FREEDOM: FPGA-Based Hardware Redaction Emulator. - Chaital G. Sathe; Yiorgos Makris; Benjamin Carrion Schafer (FCCM, 2025)

Enhancing Metrology to E-test Correlation Model Accuracy through Process Expertise Integration. - Ching-Yi Chang; Matthew Nigh; John M. Carulli; Yiorgos Makris (VTS, 2025)

A TRAP for SAT: On the Imperviousness of a Transistor-Level Programmable Fabric to Satisfiability-Based Attacks. - Aric Fowler; Mohammed Shayan; Mustafa M. Shihab; Thomas Broadfoot; Peter Beerel; Carl Sechen; Yiorgos Makris (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

Physically Secure Logic Locking With Nanomagnet Logic. - Alexander J. Edwards; Naimul Hassan; Jared Arzate; Alexander N. Chin; Dhritiman Bhattacharya; Mustafa M. Shihab; Peng Zhou; Xuan Hu 002; Jayasimha Atulasimha; Yiorgos Makris; Joseph S. Friedman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Modeling Bidirectional Switches for Enabling Logic Equivalence Checking in a Transistor-Level Programmable Fabric. - Apurva Jain; Thomas Broadfoot; Yiorgos Makris; Carl Sechen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)