C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. - Th. Haniotakis; Dimitris Nikolos; Y. Tsiatouhas (DFT, 1998)

Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. - Dimitris Nikolos; Haridimos T. Vergos; Th. Haniotakis; Y. Tsiatouhas (DATE, 1999)

A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. - Y. Tsiatouhas; Th. Haniotakis (DFT, 1999)

On Path Delay Fault Testing of Multiplexer - Based Shifters. - Haridimos T. Vergos; Dimitris Nikolos; Y. Tsiatouhas; Th. Haniotakis; Michael Nicolaidis (Great Lakes Symposium on VLSI, 1999)

Novel domino logic designs. - Th. Haniotakis; Y. Tsiatouhas; Angela Arapoyanni (ICECS, 1999)

A Versatile Built-In Self-Test Scheme for Delay Fault Testing. - Y. Tsiatouhas; Th. Haniotakis; Angela Arapoyanni; Dimitris Nikolos (DATE, 2000)

A test pattern generation unit for memory NPSF built-in self test. - A. Chrisanthopoulos; George Kamoulakos; Y. Tsiatouhas; Angela Arapoyanni (ICECS, 2000)

A state assignment algorithm for finite state machines. - Dionisis Skias; Th. Haniotakis; Y. Tsiatouhas; Angela Arapoyanni (ICECS, 2000)

New memory sense amplifier designs in CMOS technology. - Y. Tsiatouhas; A. Chrisanthopoulos; George Kamoulakos; Th. Haniotakis (ICECS, 2000)

A Compact Built-In Current Sensor for IDDQ Testing. - Y. Tsiatouhas; Th. Haniotakis; Dimitris Nikolos (IOLTW, 2000)

On Testability of Multiple Precharged Domino Logic. - Th. Haniotakis; Y. Tsiatouhas; Dimitris Nikolos; Costas Efstathiou (ISQED, 2000)

Management of charge pump circuits. - George Kamoulakos; A. Chrisanthopoulos; Y. Tsiatouhas; Angela Arapoyanni (Integr., 2000)

New test pattern generation units for NPSF oriented memory built-in self test. - A. Chrisanthopoulos; Th. Haniotakis; Y. Tsiatouhas; Angela Arapoyanni (ICECS, 2001)

A new flash memory sense amplifier in 0.18 μm CMOS technology. - A. Chrisanthopoulos; Yiannis Moisiadis; A. Varagis; Y. Tsiatouhas; Angela Arapoyanni (ICECS, 2001)

Concurrent Detection of Soft Errors Based on Current Monitoring. - Y. Tsiatouhas; Th. Haniotakis; Dimitris Nikolos; Costas Efstathiou (IOLTW, 2001)

A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. - Y. Tsiatouhas; Angela Arapoyanni; Dimitris Nikolos; Th. Haniotakis (IOLTW, 2002)

SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology. - A. Chrisanthopoulos; Y. Tsiatouhas; Angela Arapoyanni; Themistoklis Haniotakis (ISCAS (5), 2002)

Extending the Viability of IDDQ Testing in the Deep Submicron Era. - Y. Tsiatouhas; Th. Haniotakis; Dimitris Nikolos; Angela Arapoyanni (ISQED, 2002)

A new technique for IDDQ testing in nanometer technologies. - Y. Tsiatouhas; Yiannis Moisiadis; Th. Haniotakis; Dimitris Nikolos; Angela Arapoyanni (Integr., 2002)

A novel scheme for testing radio frequency voltage controlled oscillators. - Lampros Dermentzoglou; Yiorgos Tsiatouhas; Angela Arapoyanni (ICECS, 2003)

A low power NORA circuit design technique based on charge recycling. - Yiorgos Tsiatouhas; Konstantinos Limniotis; Angela Arapoyanni; Themistoklis Haniotakis (ICECS, 2003)

A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs. - Y. Tsiatouhas; Sotirios Matakias; Angela Arapoyanni; Th. Haniotakis (IOLTS, 2003)

An Embedded IDDQ Testing Architecture and Technique. - Y. Tsiatouhas; Th. Haniotakis; Angela Arapoyanni (ISQED, 2003)

A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. - A. Rao; Th. Haniotakis; Y. Tsiatouhas; V. Kaky (IOLTS, 2004)

Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . - Sotirios Matakias; Y. Tsiatouhas; Th. Haniotakis; Angela Arapoyanni (ISVLSI, 2004)

A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators. - Lampros Dermentzoglou; Y. Tsiatouhas; Angela Arapoyanni (J. Electron. Test., 2004)

A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs. - Sotirios Matakias; Y. Tsiatouhas; Angela Arapoyanni; Themistoklis Haniotakis (J. Electron. Test., 2004)

A built-in IDDQ testing circuit. - Sotirios Matakias; Yiorgos Tsiatouhas; Angela Arapoyanni; Th. Haniotakis; Guillaume Prenat; Salvador Mir (ESSCIRC, 2005)

An embedded IDDQ testing circuit and technique. - Sotirios Matakias; Yiorgos Tsiatouhas; Angela Arapoyanni; Themistoklis Haniotakis (ICECS, 2005)

Fast, Parallel Two-Rail Code Checker with Enhanced Testability. - Sotirios Matakias; Y. Tsiatouhas; Themistoklis Haniotakis; Angela Arapoyanni; Aristides Efthymiou (IOLTS, 2005)

A Built-In Self-Test Scheme for Differential Ring Oscillators. - Lampros Dermentzoglou; Y. Tsiatouhas; Angela Arapoyanni (ISQED, 2005)

The Use of Pre-Evaluation Phase in Dynamic CMOS Logic. - A. Rao; Th. Haniotakis; Y. Tsiatouhas; H. Djemil (ISVLSI, 2005)

A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism. - Andreas Floros 003; Yiorgos Tsiatouhas; Angela Arapoyanni; Themistoklis Haniotakis (ICECS, 2006)

High fan-in differential current mirror logic. - Y. Tsiatouhas; Angela Arapoyanni (ISCAS, 2006)

A Design Technique for Energy Reduction in NORA CMOS Logic. - Konstantinos Limniotis; Yiorgos Tsiatouhas; Themistoklis Haniotakis; Angela Arapoyanni (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

An Embedded Test Circuit for RF Single Ended Low Noise Amplifiers. - Lampros Dermentzoglou; Anastasios Karagounis; Aggeliki Arapoyanni; Yiorgos Tsiatouhas (ICECS, 2007)

A Scan Flip-Flop for Low-Power Scan Operation. - Yiorgos Tsiatouhas; Angela Arapoyanni; Dionisis Skias (ICECS, 2007)

A Stress-Relaxed Negative Voltage-Level Converter. - Yiorgos Tsiatouhas (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Testable Designs of Multiple Precharged Domino Circuits. - Themistoklis Haniotakis; Y. Tsiatouhas; Dimitris Nikolos; Costas Efstathiou (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Timing Error Detection and Correction by Time Dilation. - Andreas Floros 003; Yiorgos Tsiatouhas; Xrysovalantis Kavousianos (VLSI-SoC (Selected Papers), 2008)

A Current Mode, Parallel, Two-Rail Code Checker. - Sotirios Matakias; Yiorgos Tsiatouhas; Themistoklis Haniotakis; Angela Arapoyanni (IEEE Trans. Computers, 2008)

Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing. - Yiorgos Sfikas; Yiorgos Tsiatouhas (DDECS, 2009)

A Build-In Self-Test technique for RF Mixers. - Lambros Dermentzoglou; Angela Arapoyanni; Yiorgos Tsiatouhas (DDECS, 2010)

Timing error tolerance in nanometer ICs. - Stefanos Valadimas; Yiorgos Tsiatouhas; Angela Arapoyanni (IOLTS, 2010)

Memory-Less Pipeline Dynamic Circuit Design Technique. - Themistoklis Haniotakis; Zaher Owda; Yiorgos Tsiatouhas (ISVLSI, 2010)

A Receiver Circuit for Low-Swing Interconnect Schemes. - Yiannis Moisiadis; Yiorgos Tsiatouhas (ISVLSI, 2010)

A Built-In-Test Circuit for RF Differential Low Noise Amplifiers. - Lambros Dermentzoglou; Angela Arapoyanni; Yiorgos Tsiatouhas (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches. - Zhaobo Zhang; Xrysovalantis Kavousianos; Yan Luo; Yiorgos Tsiatouhas; Krishnendu Chakrabarty (ETS, 2011)

A BIST scheme for testing and repair of multi-mode power switches. - Zhaobo Zhang; Xrysovalantis Kavousianos; Yiorgos Tsiatouhas; Krishnendu Chakrabarty (IOLTS, 2011)

A Robust and Reconfigurable Multi-mode Power Gating Architecture. - Zhaobo Zhang; Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Yiorgos Tsiatouhas (VLSI Design, 2011)

Low power scan by partitioning and scan hold. - Efi Arvaniti; Yiorgos Tsiatouhas (DDECS, 2012)

Single event upset tolerance in flip-flop based microprocessor cores. - Stefanos Valadimas; Yiorgos Tsiatouhas; Angela Arapoyanni; Adrian Evans (DFT, 2012)

A novel architecture to reduce test time in march-based SRAM tests. - Ioannis Voyiatzis; Costas Efstathiou; Yiorgos Tsiatouhas; Cleo Sgouropoulou (DTIS, 2012)

Cost and power efficient timing error tolerance in flip-flop based microprocessor cores. - Stefanos Valadimas; Yiorgos Tsiatouhas; Angela Arapoyanni (ETS, 2012)

The leafs scan-chain for test application time and scan power reduction. - Maria Chalkia; Yiorgos Tsiatouhas (ICECS, 2012)

Testing wireless transceivers' RF front-ends utilizing defect-oriented BIST techniques. - Lampros Dermentzoglou; John Liaperdos; Angela Arapoyanni; Yiorgos Tsiatouhas (ICECS, 2012)

NBTI aging tolerance in pipeline based designs NBTI. - Katerina Katsarou; Yiorgos Tsiatouhas; Angela Arapoyanni (IOLTS, 2013)

Effective Timing Error Tolerance in Flip-Flop Based Core Designs. - Stefanos Valadimas; Yiorgos Tsiatouhas; Angela Arapoyanni; Petros Xarchakos (J. Electron. Test., 2013)

Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables. - John Liaperdos; Angela Arapoyanni; Y. Tsiatouhas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

New High-Speed Multioutput Carry Look-Ahead Adders. - Costas Efstathiou; Zaher Owda; Yiorgos Tsiatouhas (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Built-In Voltage Measurement Technique for the Calibration of RF Mixers. - John Liaperdos; Angela Arapoyanni; Yiorgos Tsiatouhas (IEEE Trans. Instrum. Meas., 2013)

Stuck-at fault diagnosis in scan chains. - Helen-Maria Dounavi; Yiorgos Tsiatouhas (DTIS, 2014)

Power efficient scan testing by exploiting existing error tolerance circuitry in a design. - Anthi Anastasiou; Yiorgos Tsiatouhas (ETS, 2014)

Double node charge sharing SEU tolerant latch design. - Katerina Katsarou; Yiorgos Tsiatouhas (IOLTS, 2014)

Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique. - Efi Arvaniti; Yiorgos Tsiatouhas (J. Electron. Test., 2014)

The Time Dilation Technique for Timing Error Tolerance. - Stefanos Valadimas; Andreas Floros 003; Yiorgos Tsiatouhas; Angela Arapoyanni; Xrysovalantis Kavousianos (IEEE Trans. Computers, 2014)

Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches. - Ran Wang 002; Zhaobo Zhang; Xrysovalantis Kavousianos; Yiorgos Tsiatouhas; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Layout-Based Refined NPSF Model for DRAM Characterization and Testing. - Yiorgos Sfikas; Yiorgos Tsiatouhas; Said Hamdioui (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches. - Zhaobo Zhang; Xrysovalantis Kavousianos; Krishnendu Chakrabarty; Yiorgos Tsiatouhas (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A method for the estimation of defect detection probability of analog/RF defect-oriented tests. - John Liaperdos; Angela Arapoyanni; Yiorgos Tsiatouhas (DATE, 2015)

Fast deployment of alternate analog test using Bayesian model fusion. - John Liaperdos; Haralampos-G. D. Stratigopoulos; Louay Abdallah; Yiorgos Tsiatouhas; Angela Arapoyanni; Xin Li (DATE, 2015)

On resistive open defect detection in DRAMs: The charge accumulation effect. - Yiorgos Sfikas; Yiorgos Tsiatouhas; Mottaqiallah Taouil; Said Hamdioui (ETS, 2015)

Soft error immune latch under SEU related double-node charge collection. - Katerina Katsarou; Yiorgos Tsiatouhas (IOLTS, 2015)

On the reuse of existing error tolerance circuitry for low power scan testing. - Anthi Anastasiou; Yiorgos Tsiatouhas; Angela Arapoyanni (ISCAS, 2015)

Scan chain based at-speed diagnosis in the presence of scan output compaction schemes. - Helen-Maria Dounavi; Yiorgos Tsiatouhas; Angela Arapoyanni (Panhellenic Conference on Informatics, 2015)

A current monitoring technique for IDDQ testing in digital integrated circuits. - Sotirios Matakias; Yiorgos Tsiatouhas; Angela Arapoyanni; Themistoklis Haniotakis (Integr., 2015)

Timing error mitigation in microprocessor cores. - Stefanos Valadimas; Angela Arapoyanni; Yiorgos Tsiatouhas (ICECS, 2016)

Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design. - Raghava Katreepalli; Hemanth Chemanchula; Themistoklis Haniotakis; Yiorgos Tsiatouhas (ISVLSI, 2016)

Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs. - Yiorgos Sfikas; Yiorgos Tsiatouhas (IEEE Trans. Computers, 2016)

Timing Error Tolerance in Small Core Designs for SoC Applications. - Stefanos Valadimas; Yiorgos Tsiatouhas; Angela Arapoyanni (IEEE Trans. Computers, 2016)

Periodic Bias-Temperature Instability monitoring in SRAM cells. - Yiorgos Tsiatouhas (ETS, 2017)

Variation tolerant BTI monitoring in SRAM cells. - Yiorgos Sfikas; Yiorgos Tsiatouhas (IOLTS, 2017)

BTI and HCI degradation detection in SRAM cells. - Yiorgos Sfikas; Yiorgos Tsiatouhas (MOCAST, 2017)

Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVs. - Stylianos-Georgios Papadopoulos; Vasileios Gerakis; Yiorgos Tsiatouhas; Alkis A. Hatzopoulos (PATMOS, 2017)

Low Power and High Speed Static CMOS Digital Magnitude Comparators. - Costas Efstathiou; K. Dimolikas; Christoforos Papaioannou; Yiorgos Tsiatouhas (ICECS, 2018)

Periodic Aging Monitoring in SRAM Sense Amplifiers. - Helen-Maria Dounavi; Yiorgos Sfikas; Yiorgos Tsiatouhas (IOLTS, 2018)

Aging monitoring in SRAM sense amplifiers. - Helen-Maria Dounavi; Yiorgos Sfikas; Yiorgos Tsiatouhas (MOCAST, 2018)

On the Static CMOS Implementation of Magnitude Comparators. - Costas Efstathiou; Yiorgos Tsiatouhas (PATMOS, 2019)

Monitoring of BTI and HCI Aging in SRAM Decoders. - Helen-Maria Dounavi; Yiorgos Tsiatouhas (ETS, 2020)

An Alternative Post-bond Testing Method for TSVs. - Vasileios Gerakis; Yiorgos Tsiatouhas; Alkis A. Hatzopoulos (MOCAST, 2020)

An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems. - Marina E. Plissiti; Christoforos Papaioannou; Yiorgos Sfikas; Georgios Papatheodorou; Simon-Ilias Poulis; Aristides Efthymiou; Yiorgos Tsiatouhas (MeditCom, 2021)

Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier. - Helen-Maria Dounavi; Yiorgos Sfikas; Yiorgos Tsiatouhas (J. Electron. Test., 2021)

A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs. - Vasileios Gerakis; Yiorgos Tsiatouhas; Alkis A. Hatzopoulos (J. Electron. Test., 2021)

Signal decoding in an NLOS VLC system with the presence of anti-reflective obstacles. - Christoforos Papaioannou; Marina E. Plissiti; Yiorgos Sfikas; Georgios Papatheodorou; Simon-Ilias Poulis; Aristides Efthymiou; Yiorgos Tsiatouhas (BlackSeaCom, 2022)

BTI Aging Influence on Charge Pump Circuits. - Spyridon Spyridonos; Yiorgos Tsiatouhas (MOCAST, 2022)

Efficient Dynamic Logic Magnitude Comparators. - Constantinos Efstathiou; Laura Agalioti; Yiorgos Tsiatouhas (VLSI-SoC, 2022)

SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs. - Athanasios Xynos; Vasileios Tenentes; Yiorgos Tsiatouhas (ETS, 2023)

BTI Aging Influence in SRAM-based In-Memory Computing Schemes and its Mitigation. - Christina Dilopoulou; Yiorgos Tsiatouhas (ICECS, 2023)

BTI Aging Influence and Mitigation in Neural Networks Oriented In-Memory Computing SRAMs. - Christina Dilopoulou; Yiorgos Tsiatouhas (MOCAST, 2023)

Embedded Platforms for Trusted Edge Computing Towards Quality Assurance Along the Supply Chain. - Vasileios Tenentes; Athanasios Xynos; Christos Zonios; Asimina Koutra; Christina Dilopoulou; Konstantinos Tsampiras; Yiorgos Tsiatouhas; Daniele Rossi 001 (SEEDA-CECNSM, 2023)

An aging monitoring scheme for SRAM decoders. - Helen-Maria Dounavi; Yiorgos Tsiatouhas (Integr., 2023)

Testing Algorithms for Hard to Detect Thermal Crosstalk Induced Write Disturb Faults in Phase Change Memories. - Spyridon Spyridonos; Yiorgos Tsiatouhas (DATE, 2024)

Deep Learning Based Detection of Anti-Reflective Obstacles in VLC Systems. - Marina E. Plissiti; Christoforos Papaioannou; Yiorgos Sfikas; Georgios Papatheodorou; Simon-Ilias Poulis; Aristides Efthymiou; Yiorgos Tsiatouhas (ICAIIC, 2024)

CAS-PUF: Current-Mode Array-Type Strong PUF for Secure Computing in Area Constrained SoCs. - Dimosthenis Georgoulas; Yiorgos Tsiatouhas; Vasileios Tenentes (DATE, 2025)

Efficient Tree Architecture for the Design of Static CMOS Magnitude Comparators. - Constantinos Efstathiou; John Liaperdos; Yiorgos Tsiatouhas (ISVLSI, 2025)

BTI Aging Analysis and Mitigation for Differential Input In-Memory Computing SRAMs. - Christina Dilopoulou; Yiorgos Tsiatouhas (IEEE Trans. Very Large Scale Integr. Syst., 2025)