Quasi-Static Energy Recovery Logic with Single Power-Clock Supply. - Shun Li 002; Feng Zhou; Chunhong Chen; Hua Chen; Yipin Wu (ISCAS, 2007)

A novel power noise simulation methodology for chip design using Wafer Level Chip Scale Packaging. - Yipin Wu; Zhigang Hao; Jingchun Han; Joy Tsai (VLSI-DAT, 2014)

Stack effect and logic restructuring on high Fan-in FinFETs logic gates. - Senthilkumar Jayapal; Janani Sainath Sigundey; Yipin Wu; EricT Tsai (ISIC, 2016)