A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. - Jianxun Yang; Yuyao Kong; Zhao Zhang; Zhuangzhi Liu; Jing Zhou; Yiqi Wang 005; Yonggang Liu; Chenfu Guo; Te Hu; Congcong Li; Leibo Liu; Jin Zhang; et al. (A-SSCC, 2020)

TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. - Jianxun Yang; Yuyao Kong; Zhao Zhang; Zhuangzhi Liu; Jing Zhou; Yiqi Wang 005; Yonggang Liu; Chenfu Guo; Te Hu; Congcong Li; Leibo Liu; Jin Zhang; et al. (IEEE J. Solid State Circuits, 2021)

A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. - Fengbin Tu; Yiqi Wang 005; Zihan Wu 006; Ling Liang; Yufei Ding 001; Bongjin Kim; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (ISSCC, 2022)

A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Ling Liang; Liu Liu 017; Yufei Ding 001; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (ISSCC, 2022)

GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating. - Jianxun Yang; Fengbin Tu; Yixuan Li; Yiqi Wang 005; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

MuITCIM: A 28nm $2.24 mu mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Shouyi Yin (ISSCC, 2023)

TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration. - Fengbin Tu; Yiqi Wang 005; Zihan Wu 006; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Shouyi Yin (ISSCC, 2023)

TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Ling Liang; Liu Liu 017; Yufei Ding 001; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (IEEE J. Solid State Circuits, 2023)

ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. - Fengbin Tu; Yiqi Wang 005; Zihan Wu 006; Ling Liang; Yufei Ding 001; Bongjin Kim; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (IEEE J. Solid State Circuits, 2023)

SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration. - Fengbin Tu; Yiqi Wang 005; Ling Liang; Yufei Ding 001; Leibo Liu; Shaojun Wei; Shouyi Yin; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization. - Yiqi Wang 005; Fengbin Tu; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction. - Yiqi Wang 005; Zhen He; Chenggang Zhao; Zihan Wu 006; Mingyu Gao 001; Huiming Han; Shaojun Wei; Yang Hu 001; Fengbin Tu; Shouyi Yin (VLSI Technology and Circuits, 2024)

MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Shouyi Yin (IEEE J. Solid State Circuits, 2024)

ER-DCIM: Error-Resilient Digital CIM Architecture with Run-Time MAC-Cell Error Correction. - Zhen He; Yiqi Wang 005; Zihan Wu 006; Shaojun Wei; Yang Hu 001; Fengbin Tu; Shouyi Yin (HPCA, 2025)

TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration. - Yiqi Wang 005; Zihan Wu 006; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Fengbin Tu; Shouyi Yin (IEEE J. Solid State Circuits, 2025)