An improvement of GNY logic for the reflection attacks. - Yiqiang Ding (J. Comput. Sci. Technol., 1999)

Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications. - Yiqiang Ding; Jun Yan 008; Wei Zhang 002 (J. Comput. Sci. Eng., 2009)

Improving the static real-time scheduling on multicore processors by reducing worst-case inter-thread cache interferences. - Yiqiang Ding; Wei Zhang 002 (ACM Southeast Regional Conference, 2010)

Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time. - Yiqiang Ding; Wei Zhang 002 (IEEE Trans. Computers, 2010)

Multicore-Aware Code Positioning to Improve Worst-Case Performance. - Yiqiang Ding; Wei Zhang 002 (ISORC, 2011)

Multicore-Aware Code Co-Positioning to Reduce WCET on Dual-Core Processors with Shared Instruction Caches. - Yiqiang Ding; Wei Zhang 002 (J. Comput. Sci. Eng., 2012)

Architectural time-predictability factor (ATF): a metric to evaluate time predictability of processors. - Yiqiang Ding; Wei Zhang 002 (SIGBED Rev., 2012)

Standard deviation of CPI: A new metric to evaluate architectural time predictability. - Wei Zhang 002; Yiqiang Ding (ASAP, 2013)

Hybrid SPM-cache architectures to achieve high time predictability and performance. - Wei Zhang 002; Yiqiang Ding (ASAP, 2013)

On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors. - Yiqiang Ding; Wei Zhang 002 (ISQED, 2013)

Multicore Real-Time Scheduling to Reduce Inter-Thread Cache Interferences. - Yiqiang Ding; Wei Zhang 002 (J. Comput. Sci. Eng., 2013)

Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared Caches. - Yiqiang Ding; Wei Zhang 002 (J. Comput. Sci. Eng., 2013)

Bounding Worst-Case DRAM Performance on Multicore Processors. - Yiqiang Ding; Lan Wu; Wei Zhang 002 (J. Comput. Sci. Eng., 2013)

Hop-Based Priority Scheduling to Improve Worst-Case Inter-core Communication Latency. - Yiqiang Ding; Wei Zhang 002 (EUC, 2014)

Bounding the Worst-Case Execution Time of Static NUCA Caches. - Yiqiang Ding; Wei Zhang 002 (HPCC/CSS/ICESS, 2014)

Characterizing Energy Consumption of Real-Time and Media Benchmarks on Hybrid SPM-Caches. - Lan Wu; Yiqiang Ding; Wei Zhang 002 (HPCC/CSS/ICESS, 2014)

WCET analysis of static NUCA caches. - Yiqiang Ding; Wei Zhang 002 (IPCCC, 2014)

Comparing Separate and Statically-Partitioned Caches for Time-Predictable Multicore Processors. - Lan Wu; Yiqiang Ding; Wei Zhang 002 (J. Comput. Sci. Eng., 2014)

Exploiting Standard Deviation of CPI to Evaluate Architectural Time-Predictability. - Wei Zhang 002; Yiqiang Ding (J. Comput. Sci. Eng., 2014)

Exploiting Static Non-Uniform Cache Architectures for Hard Real-Time Computing. - Yiqiang Ding; Wei Zhang 002 (J. Comput. Sci. Eng., 2015)