A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach. - Bah-Hwee Gwee; Joseph S. Chang; Yiqiong Shi; Chien-Chung Chua; Kwen-Siong Chong (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A highly efficient method for extracting FSMs from flattened gate-level netlist. - Yiqiong Shi; Chan Wai Ting; Bah-Hwee Gwee; Ye Ren (ISCAS, 2010)

Asynchronous DSP for low-power energy-efficient embedded systems. - Yiqiong Shi; Bah-Hwee Gwee; Joseph Sylvester Chang (Microprocess. Microsystems, 2011)

Extracting functional modules from flattened gate-level netlist. - Yiqiong Shi; Bah-Hwee Gwee; Ye Ren; Thet Khaing Phone; Chan Wai Ting (ISCIT, 2012)

Designing globally-asynchronous-locally-system from multi-rate Simulink model. - Yiqiong Shi; Bah-Hwee Gwee (NEWCAS, 2013)

Deep Learning for Automatic IC Image Analysis. - Xuenong Hong; Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee (DSP, 2018)

Hybrid K-Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images. - Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee; Kar-Ann Toh (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Global Template Projection and Matching Method for Training-Free Analysis of Delayered IC Images. - Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee; Kar-Ann Toh (ISCAS, 2019)

A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images. - Deruo Cheng; Yiqiong Shi; Bah-Hwee Gwee; Kar-Ann Toh; Tong Lin 001 (IEEE Intell. Syst., 2019)

Joint Anomaly Detection and Inpainting for Microscopy Images Via Deep Self-Supervised Learning. - Ling Huang; Deruo Cheng; Xulei Yang; Tong Lin 001; Yiqiong Shi; Kaiyi Yang; Bah-Hwee Gwee; Bihan Wen (ICIP, 2021)

Unsupervised Domain Adaptation with Histogram-gated Image Translation for Delayered IC Image Analysis. - Yee-Yang Tee; Deruo Cheng; Chye-Soon Chee; Tong Lin 001; Yiqiong Shi; Bah-Hwee Gwee (CoRR, 2022)

Delayered IC image analysis with template-based Tanimoto Convolution and Morphological Decision. - Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee; Kar-Ann Toh (IET Circuits Devices Syst., 2022)

Deep-learning-based X-ray CT Slice Analysis for Layout Verification in Printed Circuit Boards. - Deruo Cheng; Yiqiong Shi; Yee-Yang Tee; Jingsi Song; Xue Wang; Bihan Wen; Bah-Hwee Gwee (AICAS, 2023)

GRACER: Graph-Based Standard Cell Recognition in IC Images for Hardware Assurance. - Erdong Huang; Xuenong Hong; Tong Lin 001; Yiqiong Shi; Bah-Hwee Gwee (IECON, 2023)

SEM2GDS: A Deep-Learning Based Framework To Detect Malicious Modifications In IC Layout. - Tong Lin 001; Yiqiong Shi; Bah-Hwee Gwee (ISCAS, 2023)

Patch-Based Adversarial Training for Error-Aware Circuit Annotation of Delayered IC Images. - Yee-Yang Tee; Xuenong Hong; Deruo Cheng; Chye-Soon Chee; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning. - Xuenong Hong; Tong Lin 001; Yiqiong Shi; Bah-Hwee Gwee (IEEE Trans. Artif. Intell., 2023)

MLConnect: A Machine Learning Based Connection Prediction Framework for Error Correction in Recovered Circuit. - Xuenong Hong; Zilong Hu; Han Zhang; Yee-Yang Tee; Tong Lin 001; Yiqiong Shi; Deruo Cheng; Bah-Hwee Gwee (ISCAS, 2024)

Unpaired Synthesis of IC Scanning Electron Microscopy Images with Structural Constraints. - Luyun Li; Deruo Cheng; Yiqiong Shi; Bah-Hwee Gwee (IST, 2024)

Integrated Circuit Mask-Generative Adversarial Network for Circuit Annotation With Targeted Data Augmentation. - Yee-Yang Tee; Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee (IEEE Intell. Syst., 2024)

Multiple Hypothesis Testing for SEM Image Processing: A Case Study on Standard Cell Partition. - Xiaoyu Ma; Yizhen Li; Feng Ji; Tong Lin 001; Yiqiong Shi; Deruo Cheng; Bah-Hwee Gwee (ISCAS, 2025)

SSRNet: Few-shot IC Segmentation in Automated PCB Image Processing. - Yuhang Wang; Xinrui Wang 004; Deruo Cheng; Tong Lin 001; Feng Ji; Yiqiong Shi; Bah-Hwee Gwee (ISCAS, 2025)

Long-Short-GNN: A Novel Graph Neural Network for Detecting FPGA IP Circuits for Hardware Assurance. - Heyi Zhang; Tong Lin 001; Feng Ji; Deruo Cheng; Yiqiong Shi; Bah-Hwee Gwee (ISCAS, 2025)

GNNReveal: A Novel Graph-Neural-Network-Based Attack Method for Integrated Circuit Logic Gate Decamouflaging. - Xuenong Hong; Yee-Yang Tee; Zilong Hu; Tong Lin 001; Yiqiong Shi; Deruo Cheng; Bah-Hwee Gwee (IEEE Intell. Syst., 2025)

Data-Efficient Deep Learning for Printed Circuit Board Defect Detection Using X-Ray Images. - Hong Duc Nguyen; Deruo Cheng; Xinrui Wang 004; Yiqiong Shi; Bihan Wen (IEEE Trans. Instrum. Meas., 2025)