A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers. - Chen Yang 005; Yishuo Meng; Kaibo Huo; Jiawei Xi; Kuizhi Mei (IEEE Trans. Very Large Scale Integr. Syst., 2022)

An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method. - Yuheng Xia; Yishuo Meng; Siwei Xiang; Jianfei Wang 003; Chen Yang 005 (ICTA, 2023)

POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection. - Jia Hou; Jingyu Zhang; Qi Chen; Siwei Xiang; Yishuo Meng; Jianfei Wang 003; Cimang Lu; Chen Yang 005 (Inf., 2023)

TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Yishuo Meng; Yang Su 003 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow. - Yishuo Meng; Chen Yang 005; Siwei Xiang; Jianfei Wang 003; Kuizhi Mei; Li Geng (IEEE Trans. Very Large Scale Integr. Syst., 2023)

LSTM-CRP: Algorithm-Hardware Co-Design and Implementation of Cache Replacement Policy Using Long Short-Term Memory. - Yizhou Wang 004; Yishuo Meng; Jiaxing Wang; Chen Yang 005 (Big Data Cogn. Comput., 2024)

An Efficient and Scalable FHE-Based PDQ Scheme: Utilizing FFT to Design a Low Multiplication Depth Large-Integer Comparison Algorithm. - Fahong Zhang 002; Chen Yang 005; Rui Zong; Xinran Zheng; Jianfei Wang 003; Yishuo Meng (IEEE Trans. Inf. Forensics Secur., 2024)

A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Yishuo Meng; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks. - Chen Yang 005; Yishuo Meng; Jiawei Xi; Siwei Xiang; Jianfei Wang 003; Kuizhi Mei (IEEE Trans. Very Large Scale Integr. Syst., 2024)

LMS-Based Background Calibration of Bit Weights in SAR ADC Using Reinforcement Learning Optimization. - Xinyan Song; Qiao Meng; Yujia Huang; Chenchen Zong; Yishuo Meng (Circuits Syst. Signal Process., 2024)

Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units. - Chen Yang 005; Yaoyao Yang; Yishuo Meng; Kaibo Huo; Siwei Xiang; Jianfei Wang 003; Li Geng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Jia Hou; Yishuo Meng; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

ALSCA: A Large-Scale Sparse CNN Accelerator Using Position-First Dataflow and Input Channel Merging Approach. - Yishuo Meng; Siwei Xiang; Jianfei Wang 003; Jia Hou; Chen Yang 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data. - Jianfei Wang 003; Jia Hou; Fahong Zhang 002; Yishuo Meng; Yang Su 003; Chen Yang 005 (ASP-DAC, 2025)

An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm. - Jianfei Wang 003; Jia Hou; Fahong Zhang 002; Yishuo Meng; Yang Su 003; Chen Yang 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption. - Jianfei Wang 003; Chen Yang 005; Jia Hou; Fahong Zhang 002; Yishuo Meng; Yang Su 003; Leibo Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A High-Throughput and Flexible CNN Accelerator Based on Mixed-Radix FFT Method. - Yishuo Meng; Junfeng Wu; Siwei Xiang; Jianfei Wang 003; Jia Hou; Zhijie Lin; Chen Yang 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme. - Jianfei Wang 003; Chen Yang 005; Yishuo Meng; Fahong Zhang 002; Jia Hou; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline. - Jia Hou; Jianfei Wang 003; Yishuo Meng; Fahong Zhang 002; Yang Su 003; Chen Yang 005 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Rethinking the Designing of Convolution Engine for Reconfigurable CNN Accelerator Using Sparse-Based Design Scheme. - Yishuo Meng; Jianfei Wang 003; Siwei Xiang; Jia Hou; Zhijie Lin; Kuizhi Mei; Chen Yang 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)