A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching. - Yitao Ma; Tetsuo Endoh; Tadashi Shibata (ISOCC, 2011)

An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications. - Yitao Ma; Tadashi Shibata; Tetsuo Endoh (ISCAS, 2013)

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. - Takahiro Hanyu; Tetsuo Endoh; Daisuke Suzuki; Hiroki Koike; Yitao Ma; Naoya Onizawa; Masanori Natsui; Shoji Ikeda; Hideo Ohno (Proc. IEEE, 2016)

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (ISSCC, 2019)

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (IEEE J. Solid State Circuits, 2019)

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (VLSI Circuits, 2020)

Normalization-Based Validity Index of Adaptive K-Means Clustering for Multi-Solution Application. - Tao Li 005; Yitao Ma; Tetsuo Endoh (IEEE Access, 2020)

A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate. - Tao Li 005; Yitao Ma; Tetsuo Endoh (IEEE Access, 2020)

FPGA Implementation of Real-Time Pedestrian Detection Using Normalization-Based Validation of Adaptive Features Clustering. - Tao Li 005; Yitao Ma; Hui Shen; Tetsuo Endoh (IEEE Trans. Veh. Technol., 2020)

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (IEEE J. Solid State Circuits, 2021)

Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT. - Tao Li 005; Yitao Ma; Ko Yoshikawa; Osamu Nomura; Tetsuo Endoh (IEEE Trans. Ind. Informatics, 2022)

Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator. - Tao Li 005; Yitao Ma; Ko Yoshikawa; Tetsuo Endoh (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3. - Tao Li 005; Yitao Ma; Tetsuo Endoh (Neural Comput. Appl., 2023)

Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator". - Tao Li 005; Yitao Ma; Ko Yoshikawa; Tetsuo Endoh (IEEE Trans. Very Large Scale Integr. Syst., 2023)

From Algorithm to Module: Adaptive and Energy-Efficient Quantization Method for Edge Artificial Intelligence in IoT Society. - Tao Li 005; Yitao Ma; Tetsuo Endoh (IEEE Trans. Ind. Informatics, 2023)