Floorplanning with graph attention. - Yiting Liu 002; Ziyi Ju; Zhengming Li; Mingzhi Dong; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang (DAC, 2022)

GraphPlanner: Floorplanning with Graph Neural Network. - Yiting Liu 002; Ziyi Ju; Zhengming Li; Mingzhi Dong; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang 001 (ACM Trans. Design Autom. Electr. Syst., 2023)

Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model. - Zihao Chen; Jiangli Huang; Yiting Liu 002; Fan Yang 001; Li Shang 001; Dian Zhou; Xuan Zeng 001 (DAC, 2024)

The Power of Graph Signal Processing for Chip Placement Acceleration. - Yiting Liu 002; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang 001 (ICCAD, 2024)

Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement. - Hongyang Pan; Cunqing Lan; Yiting Liu 002; Zhiang Wang; Li Shang 001; Xuan Zeng 001; Fan Yang 001; Keren Zhu 001 (ICCAD, 2024)

Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. - Yiting Liu 002; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Use Cases and Deployment of ML in IC Physical Design. - Amur Ghose; Andrew B. Kahng; Sayak Kundu; Yiting Liu 002; Bodhisatta Pramanik; Zhiang Wang; Dooseok Yoon (ASP-DAC, 2025)

Invited: IEEE DATC RDF-2025: Enabling an EDA Research Ecosystem. - Vidya A. Chhabria; Amur Ghose; Vikram Gopalakrishnan; Andrew B. Kahng; Sayak Kundu; Yiting Liu 002; Zhiang Wang; Bing-Yue Wu (ICCAD, 2025)

Recursive Learning-Based Virtual Buffering for Analytical Global Placement. - Andrew B. Kahng; Yiting Liu 002; Zhiang Wang (MLCAD, 2025)

The Power of Graph Signal Processing for Chip Placement Acceleration. - Yiting Liu 002; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang (CoRR, 2025)

An Efficient Placement Speedup Technique Based on Graph Signal Processing. - Yiting Liu 002; Hai Zhou 001; Jia Wang 003; Fan Yang 001; Xuan Zeng 001; Li Shang 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Invited: Post-Placement Buffering and Sizing Contest. - Andrew B. Kahng; Seokhyeong Kang; Sayak Kundu; Yiting Liu 002; Davit Markarian; Seonghyeon Park; Zhiang Wang (ISPD, 2026)