GPE: A New Representation for VLSI Floorplan Problem. - Chang-Tzu Lin; De-Sheng Chen; Yiwen Wang 003 (ICCD, 2002)

Non-slicing floorplans with boundary constraints using generalized polish expression. - De-Sheng Chen; Chang-Tzu Lin; Yiwen Wang 003 (ASP-DAC, 2003)

Robust fixed-outline floorplanning through evolutionary search. - Chang-Tzu Lin; De-Sheng Chen; Yiwen Wang 003 (ASP-DAC, 2004)

Fast multilevel floorplanning for large scale modules. - Ching-Chung Hu; De-Sheng Chen; Yiwen Wang 003 (ISCAS (5), 2004)

Modem floorplanning with abutment and fixed-outline constraints. - Chang-Tzu Lin; De-Sheng Chen; Yiwen Wang 003; Hsin-Hsien Ho (ISCAS (6), 2005)

Modern Floorplanning with Boundary and Fixed-outline Constraints via Genetic Clustering Algorithm. - Chang-Tzu Lin; De-Sheng Chen; Yiwen Wang 003 (J. Circuits Syst. Comput., 2006)

Noise-Aware Floorplanning for Fast Power Supply Network Design. - Chang-Tzu Lin; Tai-Wei Kung; De-Sheng Chen; Yiwen Wang 003; Ching-Hwa Cheng (ISCAS, 2007)

Application-Specific Instruction Generation for SOC Processors. - Shengjyi Yang; Chijie Lin; Chiuyun Hung; Jiying Wu; Yiwen Wang 003 (ISCAS, 2007)

Fixed-outline floorplanning using robust evolutionary search. - De-Sheng Chen; Chang-Tzu Lin; Yiwen Wang 003; Ching-Hwa Cheng (Eng. Appl. Artif. Intell., 2007)

Performance Improvement using Application-Specific Instructions under Hardware Constraints. - Chijie Lin; Jiying Wu; Jerung Shiu; Chiuyun Hung; De-Sheng Chen; Yiwen Wang 003 (ICESS, 2008)

Memory Models for an Application-Specific Instruction-set Processor Design Flow. - Jiying Wu; Chijie Lin; Desheng Chen; Yiwen Wang 003 (ICESS, 2008)

Application Specific Instruction Set Exploration on VLIW Architectures. - Chengpin Tseng; Chiuyun Hung; De-Sheng Chen; Kuei-Chung Chang; Yiwen Wang 003 (ESA, 2010)