Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory. - Juejian Wu; Yixin Xu 001; Bowen Xue; Yu Wang 002; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ASP-DAC, 2020)

Hardware Functional Obfuscation With Ferroelectric Active Interconnects. - Tongguang Yu; Yixin Xu 001; Shan Deng; Zijian Zhao 001; Nicholas Jao; You Sung Kim; Stefan Dünkel; Sven Beyer; Kai Ni 004; Sumitha George; Vijaykrishnan Narayanan (CoRR, 2021)

CMOS-Compatible Ising Machines built using Bistable Latches Coupled through Ferroelectric Transistor Arrays. - Antik Mallick; Zijian Zhao 001; Mohammad Khairul Bashar; Shamiul Alam; Md. Mazharul Islam 006; Yi Xiao 008; Yixin Xu 001; Ahmedullah Aziz; Vijaykrishnan Narayanan; Kai Ni 004; Nikhil Shukla (CoRR, 2022)

ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key. - Jianfeng Wang; Zhonghao Chen; Jiahao Zhang; Yixin Xu 001; Tongguang Yu; Enze Ye; Ziheng Zheng; Huazhong Yang; Sumitha George; Yongpan Liu; Vijaykrishnan Narayanan; Xueqing Li 002 (CoRR, 2022)

Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines. - Yixin Xu 001; Zijian Zhao 001; Yi Xiao 008; Tongguang Yu; Halid Mulaosmanovic; Dominik Kleimaier; Stefan Dünkel; Sven Beyer; Xiao Gong; Rajiv V. Joshi; X. Sharon Hu; Shixian Wen; et al. (CoRR, 2022)

WeightLock: A Mixed-Grained Weight Encryption Approach Using Local Decrypting Units for Ciphertext Computing in DNN Accelerators. - Jianfeng Wang; Zhonghao Chen; Yiming Chen; Yixin Xu 001; Tianyi Wang; Yao Yu; Vijaykrishnan Narayanan; Sumitha George; Huazhong Yang; Xueqing Li 002 (AICAS, 2023)

Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM. - Mingyen Lee; Wenjun Tang; Yiming Chen; Juejian Wu; Hongtao Zhong; Yixin Xu 001; Yongpan Liu; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (DAC, 2023)

ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory. - Hongtao Zhong; Zhonghao Chen; Wenqin Huangfu; Chen Wang; Yixin Xu 001; Tianyi Wang; Yao Yu; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (DAC, 2023)

Lowering Latency of Embedded Memory by Exploiting In-Cell Victim Cache Hierarchy Based on Emerging Multi-Level Memory Devices. - Juejian Wu; Tianyu Liao; Taixin Li; Yixin Xu 001; Vijaykrishnan Narayanan; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ICCAD, 2023)

A Compact Ferroelectric 2T-(n+1)C Cell to Implement AND-OR Logic in Memory. - Yi Xiao 008; Yixin Xu 001; Shan Deng; Zijian Zhao 001; Sumitha George; Kai Ni 004; Vijaykrishnan Narayanan (ISVLSI, 2023)

Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks. - Hongtao Zhong; Yu Zhu; Longfei Luo; Taixin Li; Chen Wang; Yixin Xu 001; Tianyi Wang; Yao Yu; Vijaykrishnan Narayanan; Yongpan Liu; Liang Shi 001; Huazhong Yang; et al. (ISVLSI, 2023)

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET. - Zijian Zhao 001; Shan Deng; Swetaki Chatterjee; Zhouhang Jiang; Muhammad Shaffatul Islam; Yi Xiao 008; Yixin Xu 001; Scott Meninger; Mohamed Mohamed 011; Rajiv V. Joshi; Yogesh Singh Chauhan; Halid Mulaosmanovic; et al. (CoRR, 2023)

Embedding Security into Ferroelectric FET Array via In-Situ Memory Operation. - Yixin Xu 001; Yi Xiao 008; Zijian Zhao 001; Franz Müller 001; Alptekin Vardar; Xiao Gong; Sumitha George; Thomas Kämpfe; Vijaykrishnan Narayanan; Kai Ni 004 (CoRR, 2023)

FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge. - Wenjun Tang; Mingyen Lee; Juejian Wu; Yixin Xu 001; Yao Yu; Yongpan Liu; Kai Ni 004; Yu Wang 002; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

REMNA: Variation-Resilient and Energy-Efficient MLC FeFET Computing-in-Memory Using NAND Flash-Like Read and Adaptive Control. - Taixin Li; Hongtao Zhong; Yixin Xu 001; Vijaykrishnan Narayanan; Kai Ni 004; Huazhong Yang; Thomas Kämpfe; Xueqing Li 002 (ICCAD, 2024)

Compact Multiplexer Design with Multi-threshold Ferroelectric FETs. - Sanwar Ahmed Ovy; Md Ashraful Islam Romel; Yi Xiao 008; Yixin Xu 001; Kai Ni 004; Sumitha George (ISVLSI, 2024)

ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories. - Taixin Li; Boran Sun; Hongtao Zhong; Yixin Xu 001; Vijaykrishnan Narayanan; Liang Shi 001; Tianyi Wang; Yao Yu; Thomas Kämpfe; Kai Ni 004; Huazhong Yang; Xueqing Li 002 (ACM Trans. Design Autom. Electr. Syst., 2024)

A Module-Level Configuration Methodology for Programmable Camouflaged Logic. - Jianfeng Wang; Zhonghao Chen; Jiahao Zhang; Yixin Xu 001; Tongguang Yu; Ziheng Zheng; Enze Ye; Sumitha George; Huazhong Yang; Yongpan Liu; Kai Ni 004; Vijaykrishnan Narayanan; et al. (ACM Trans. Design Autom. Electr. Syst., 2024)

A Study on the Impact of Temperature-Dependent Ferroelectric Switching Behavior in 3D Memory Architecture. - Varun Darshana Parekh; Yi Xiao 008; Yixin Xu 001; Zijian Zhao 001; Zhouhang Jiang; Rudra Biswas; Sumitha George; Kai Ni 004; Vijaykrishnan Narayanan (VLSID, 2025)