An ADPLL Design Model Based on LoRa IoT Application. - Yiyun Mao; Haoyuan Gao; Dejian Li; Hao Xu 005; Na Yan (ASICON, 2023)

Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL. - Yizhuo Wang; Jiahe Shi; Hao Xu 005; Shujiang Ji; Yiyun Mao; Tenghao Zou; Jun Tao 001; Hao Min; Na Yan (IEEE J. Solid State Circuits, 2023)

An All-Digital Spread-Spectrum Clock Generator With Feedforward Gain Calibration for LPWAN Chirp Transmission System. - Yiyun Mao; Haoyuan Gao; Jin Shao; Xinyi Lin; Peifang Wu; Ping Lu; Hao Xu 005; Na Yan (IEEE Trans. Circuits Syst. II Express Briefs, 2025)