A novel SPICE circuit model of electrostatic discharge (ESD) generator. - Jian Cao 002; Yize Wang; Yuan Wang 001; Guangyi Lu; Xing Zhang 002 (IEICE Electron. Express, 2016)

Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process. - Guangyi Lu; Yuan Wang 001; Yize Wang; Xing Zhang 002 (ISCAS, 2017)

A novel TLP-based method to deliver IEC 61000-4-2 ESD stress. - Yize Wang; Yuan Wang 001; Guangyi Lu; Jian Cao 002; Xing Zhang 002 (IEICE Electron. Express, 2017)

Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness. - Yuan Wang 001; Guangyi Lu; Yize Wang; Xing Zhang 002 (IEICE Trans. Electron., 2017)

Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. - Guangyi Lu; Yuan Wang 001; Lizhong Zhang; Yize Wang; Ru Huang 001; Xing Zhang 002 (ISCAS, 2018)

Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection. - Lizhong Zhang; Yuan Wang 001; Yize Wang; Xing Zhang 002; Yandong He (Sci. China Inf. Sci., 2019)

A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics. - Yize Wang; Guangyi Lu; Yuan Wang 001 (IEEE Access, 2020)

Data-Driven Robust Congestion Pricing. - Yize Wang; Dario Paccagnan (CDC, 2022)

A Novel Low-Leakage ESD Power Clamp Circuit with Adjustable Transient Response Time. - Zilong Shen; Yize Wang; Xing Zhang 002; Yuan Wang 001 (ISCAS, 2022)

QuickPose: Real-time Multi-view Multi-person Pose Estimation in Crowded Scenes. - Zhize Zhou; Qing Shuai; Yize Wang; Qi Fang; Xiaopeng Ji; Fashuai Li; Hujun Bao; Xiaowei Zhou 001 (SIGGRAPH (Conference Paper Track), 2022)

A Hybrid Model Based on Superpixel Entropy Discrimination for PolSAR Image Classification. - Jili Sun; Lingdong Geng; Yize Wang (Remote. Sens., 2022)

A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation. - Zilong Shen; Yize Wang; Yunhao Li; Xing Zhang 002; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 65nm 100MS/s-400MS/s Multi-Column SAR/SS ADC with Reconfigurable 2-8 Bit Resolution for Optical and In-memory Computing. - Anying Jiang; Ye Lin; Jiayuan Chen; Wenhe Yin; Yize Wang; Mingqian Yang; Li Du; Yuan Du (ISCAS, 2025)