A Low Power and variation-Insensitive Current-Mode Signaling Scheme. - Xinsheng Wang; Yizhe Hu; Liang Han; Jinghu Li; Chenxu Wang; Mingyan Yu (J. Circuits Syst. Comput., 2013)

A modeling approach for mixed-mode FMCW synthesizer allowing frequency error analysis. - Yizhe Hu; Wei Li (ISCAS, 2015)

A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner. - Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (ESSCIRC, 2017)

A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path. - Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2018)

DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization. - Vivek Govindaraj; Jianglin Du; Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (APCCAS, 2019)

A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS. - Jianglin Du; Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (CICC, 2019)

28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications. - Zhong Gao; Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (NEWCAS, 2019)

Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators. - Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. - Yizhe Hu; Xi Chen 070; Teerachot Siriburanon; Jianglin Du; Zhong Gao; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (ISSCC, 2020)

A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. - Jianglin Du; Teerachot Siriburanon; Xi Chen 070; Yizhe Hu; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (VLSI Circuits, 2021)

A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. - Jianglin Du; Teerachot Siriburanon; Yizhe Hu; Vivek Govindaraj; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2021)

Oscillator Flicker Phase Noise: A Tutorial. - Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Compact 0.2-0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise Over Wide Tuning Range. - Jianglin Du; Yizhe Hu; Teerachot Siriburanon; Enis Kobal; Philip Quinlan; Anding Zhu; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2022)

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. - Yizhe Hu; Xi Chen 070; Teerachot Siriburanon; Jianglin Du; Vivek Govindaraj; Anding Zhu; Robert Bogdan Staszewski (IEEE J. Solid State Circuits, 2022)

Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators. - Xi Chen 070; Yizhe Hu; Teerachot Siriburanon; Jianglin Du; Robert Bogdan Staszewski; Anding Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial. - Yizhe Hu; Teerachot Siriburanon; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM. - Weichen Tao; Weichen Zhao; Robert Bogdan Staszewski; Fujiang Lin; Yizhe Hu (VLSI Technology and Circuits, 2023)

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness. - Xi Chen 070; Yizhe Hu; Teerachot Siriburanon; Jianglin Du; Robert Bogdan Staszewski; Anding Zhu (IEEE J. Solid State Circuits, 2023)

A 25Gbps Single-Ended to Differential Low-Noise Transimpedance Amplifier in 45nm SOI for High-Speed Optical Transceivers. - Juncheng Deng; Luyao Yuan; Zeyu Zhou; Jinfeng Xie; Ahmed Wahba; Ping Ma; Yizhe Hu; Fujiang Lin; C. Patrick Yue; Liheng Lou (TENCON, 2024)

A 0.0022 mm2, 2 GS/s Resettable VCO-Based ADC With-out Quantization Noise Shaping. - Tao Lu; Zixiang Liu; Hao Yang; Sai-Weng Sin; Robert Bogdan Staszewski; Fujiang Lin; Liheng Lou; Yizhe Hu (CICC, 2025)

A 14-bit 750 MS/s energy-efficient pipelined ADC for MEMS LiDAR system. - Yizhe Hu; Lili Lang; Yemin Dong (Microelectron. J., 2025)

A Charge-Domain Fractional-N ADPLL Based on Charge-Steering Sampling. - Weichen Tao; Yuhao Yang; Weiyi Chen; Robert Bogdan Staszewski; Yizhe Hu (IEEE J. Solid State Circuits, 2025)