A PVT-insensitive self-dithered TDC design by utilizing a ΔΣ DLL. - Yizhi Han; Woogeun Rhee; Zhihua Wang 001 (MWSCAS, 2012)

A 3.5-4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDC. - Wei Zhang 078; Yizhi Han; Fei Chen 006; Bo Zhou 008; Xican Chen; Woogeun Rhee; Zhihua Wang 001 (VLSI-DAT, 2014)

A PSRR Enhancing Method for GRO TDC Based Clock Generation Systems. - Yutao Liu; Yizhi Han; Woogeun Rhee; Tae-Young Oh; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)