Offset-trimming bit-line sensing scheme for gigabit-scale DRAM's. - Jung-Won Sub; Kwang-Myoung Rho; Chan-Kwang Park; Yo-Hwan Koh (IEEE J. Solid State Circuits, 1996)

A 48nm 32Gb 8-level NAND flash memory with 5.5MB/s program throughput. - Seung-Ho Chang; Sok-Kyu Lee; Seong-Je Park; Min-Joong Jung; Jung-Chul Han; In-Soo Wang; Kyu-Hee Lim; Jung-Hwan Lee; Ji-Hwan Kim; Won-Kyung Kang; Tai-Kyu Kang; Hee-Su Byun; et al. (ISSCC, 2009)

A 32Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes in 32nm CMOS. - Changhyuk Lee; Sok-Kyu Lee; Sunghoon Ahn; Jinhaeng Lee; Wonsun Park; Yongdeok Cho; Chaekyu Jang; Chulwoo Yang; Sanghwa Chung; In-Suk Yun; Byoungin Joo; Byoungkwan Jeong; et al. (ISSCC, 2010)

A 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOS. - Tae-yun Kim; Sang-Don Lee; Jin-su Park; Ho-youb Cho; Byoung-sung You; Kwang-ho Baek; Jae-ho Lee; Chang-won Yang; Misun Yun; Min-su Kim; Jongwoo Kim; Eun-seong Jang; et al. (ISSCC, 2011)

A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS. - Changhyuk Lee; Sok-Kyu Lee; Sunghoon Ahn; Jinhaeng Lee; Wonsun Park; Yongdeok Cho; Chaekyu Jang; Chulwoo Yang; Sanghwa Chung; In-Suk Yun; Byoungin Joo; Byoungkwan Jeong; et al. (IEEE J. Solid State Circuits, 2011)