Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits. - Kuan-Ying Chiang; Yu-Hao Ho; Yo-Wei Chen; Cheng-Sheng Pan; James Chien-Mo Li (ATS, 2015)

Robust test pattern generation for hold-time faults in nanometer technologies. - Yu-Hao Ho; Yo-Wei Chen; Chih-Ming Chang; Kai-Chieh Yang; James Chien-Mo Li (VLSI-DAT, 2017)