User-Level Communication in a System with Gang Scheduling. - Yoav Etsion; Dror G. Feitelson (IPDPS, 2001)

Effects of clock resolution on the scheduling of interactive and soft real-time processes. - Yoav Etsion; Dan Tsafrir; Dror G. Feitelson (SIGMETRICS, 2003)

Desktop scheduling: how can we know what the user wants? - Yoav Etsion; Dan Tsafrir; Dror G. Feitelson (NOSSDAV, 2004)

System noise, OS clock ticks, and fine-grained parallel applications. - Dan Tsafrir; Yoav Etsion; Dror G. Feitelson; Scott Kirkpatrick (ICS, 2005)

Modeling User Runtime Estimates. - Dan Tsafrir; Yoav Etsion; Dror G. Feitelson (JSSPP, 2005)

Process prioritization using output production: Scheduling for multimedia. - Yoav Etsion; Dan Tsafrir; Dror G. Feitelson (ACM Trans. Multim. Comput. Commun. Appl., 2006)

L1 Cache Filtering Through Random Selection of Memory References. - Yoav Etsion; Dror G. Feitelson (PACT, 2007)

Fine grained kernel logging with KLogger: experience and insights. - Yoav Etsion; Dan Tsafrir; Scott Kirkpatrick; Dror G. Feitelson (EuroSys, 2007)

Secretly Monopolizing the CPU Without Superuser Privileges. - Dan Tsafrir; Yoav Etsion; Dror G. Feitelson (USENIX Security Symposium, 2007)

Probabilistic Prediction of Temporal Locality. - Yoav Etsion; Dror G. Feitelson (IEEE Comput. Archit. Lett., 2007)

Fine-grain analysis of common coupling and its application to a Linux case study. - Dror G. Feitelson; Tokunbo O. S. Adeshiyan; Daniel Balasubramanian; Yoav Etsion; Gabor Madl; Esteban Osses; Sameer Singh 001; Karlkim Suwanmongkol; Minhui Xie; Stephen R. Schach (J. Syst. Softw., 2007)

Backfilling Using System-Generated Predictions Rather than User Runtime Estimates. - Dan Tsafrir; Yoav Etsion; Dror G. Feitelson (IEEE Trans. Parallel Distributed Syst., 2007)

The skewed distribution of working sets : leveraging randomness for cache design (ההתפלגות המוטה של זיכרון עבודה.). - Yoav Etsion (2008)

A global scheduling framework for virtualization environments. - Yoav Etsion; Tal Ben-Nun; Dror G. Feitelson (IPDPS, 2009)

Can Manycores Support the Memory Requirements of Scientific Applications? - Milan Pavlovic; Yoav Etsion; Alex Ramírez (ISCA Workshops, 2010)

Task Superscalar: An Out-of-Order Task Pipeline. - Yoav Etsion; Felipe Cabarcas; Alejandro Rico; Alex Ramírez; Rosa M. Badia; Eduard Ayguadé; Jesús Labarta; Mateo Valero (MICRO, 2010)

Interleaving granularity on high bandwidth memory architecture for CMPs. - Felipe Cabarcas; Alejandro Rico; Yoav Etsion; Alex Ramírez (ICSAMOS, 2010)

Design and implementation of a generic resource sharing virtual time dispatcher. - Tal Ben-Nun; Yoav Etsion; Dror G. Feitelson (SYSTOR, 2010)

DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory. - Carlos Villavieja; Vasileios Karakostas; Lluís Vilanova; Yoav Etsion; Alex Ramírez; Avi Mendelson; Nacho Navarro; Adrián Cristal; Osman S. Unsal (PACT, 2011)

FELI: HW/SW Support for On-Chip Distributed Shared Memory in Multicores. - Carlos Villavieja; Yoav Etsion; Alex Ramírez; Nacho Navarro (Euro-Par (1), 2011)

On the memory system requirements of future scientific applications: Four case-studies. - Milan Pavlovic; Yoav Etsion; Alex Ramírez (IISWC, 2011)

Trace-driven simulation of multithreaded applications. - Alejandro Rico; Alejandro Duran; Felipe Cabarcas; Yoav Etsion; Alex Ramírez; Mateo Valero (ISPASS, 2011)

Implementation of a hierarchical N-body simulator using the Ompss programming model. - Miquel Pericàs; Xavier Martorell; Yoav Etsion (IA3@SC, 2011)

On the simulation of large-scale architectures using multiple application abstraction levels. - Alejandro Rico; Felipe Cabarcas; Carlos Villavieja; Milan Pavlovic; Augusto Vega; Yoav Etsion; Alex Ramírez; Mateo Valero (ACM Trans. Archit. Code Optim., 2012)

Exploiting Core Working Sets to Filter the L1 Cache with Random Sampling. - Yoav Etsion; Dror G. Feitelson (IEEE Trans. Computers, 2012)

Analysis of the Task Superscalar Architecture Hardware Design. - Fahimeh Yazdanpanah; Daniel Jiménez-González; Carlos Álvarez-Martínez; Yoav Etsion; Rosa M. Badia (ICCS, 2013)

CODOMs: Protecting software with Code-centric memory Domains. - Lluís Vilanova; Muli Ben-Yehuda; Nacho Navarro; Yoav Etsion; Mateo Valero (ISCA, 2014)

Single-graph multiple flows: Energy efficient design alternative for GPGPUs. - Dani Voitsechov; Yoav Etsion (ISCA, 2014)

Loop-Aware Memory Prefetching Using Code Block Working Sets. - Adi Fuchs; Shie Mannor; Uri C. Weiser; Yoav Etsion (MICRO, 2014)

O-structures: semantics for versioned memory. - Eran Gilad; Eric W. Mackay; Mark Oskin; Yoav Etsion (MSPC@PLDI, 2014)

Memristor-Based Multithreading. - Shahar Kvatinsky; Yuval H. Nacson; Yoav Etsion; Eby G. Friedman; Avinoam Kolodny; Uri C. Weiser (IEEE Comput. Archit. Lett., 2014)

Hybrid Dataflow/von-Neumann Architectures. - Fahimeh Yazdanpanah; Carlos Álvarez-Martínez; Daniel Jiménez-González; Yoav Etsion (IEEE Trans. Parallel Distributed Syst., 2014)

Semantic locality and context-based prefetching using reinforcement learning. - Leeor Peled; Shie Mannor; Uri C. Weiser; Yoav Etsion (ISCA, 2015)

Control flow coalescing on a hybrid dataflow/von Neumann GPGPU. - Dani Voitsechov; Yoav Etsion (MICRO, 2015)

NeSC: Self-virtualizing nested storage controller. - Yonatan Gottesman; Yoav Etsion (MICRO, 2016)

Flexible Caching in Trie Joins. - Oren Kalinsky; Yoav Etsion; Benny Kimelfeld (EDBT, 2017)

Direct Inter-Process Communication (dIPC): Repurposing the CODOMs Architecture to Accelerate IPC. - Lluís Vilanova; Marc Jordà; Nacho Navarro; Yoav Etsion; Mateo Valero (EuroSys, 2017)

DFiant: A dataflow hardware description language. - Oron Port; Yoav Etsion (FPL, 2017)

Towards a Deterministic Fine-Grained Task Ordering Using Multi-Versioned Memory. - Eran Gilad; Tehila Mayzels; Elazar Raab; Mark Oskin; Yoav Etsion (SBAC-PAD, 2017)

DATS - Data Containers for Web Applications. - Casen Hunger; Lluís Vilanova; Charalampos Papamanthou; Yoav Etsion; Mohit Tiwari (ASPLOS, 2018)

LEGaTO: towards energy-efficient, secure, fault-tolerant toolset for heterogeneous computing. - Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel Jiménez-González; Carlos Álvarez 001; Behzad Salami 001; Sergi Madonar; Miquel Pericàs; Pedro Trancoso; et al. (CF, 2018)

Snapshot-Based Synchronization: A Fast Replacement for Hand-over-Hand Locking. - Eran Gilad; Trevor Brown 001; Mark Oskin; Yoav Etsion (Euro-Par, 2018)

Architectural Support for Unlimited Memory Versioning and Renaming. - Eran Gilad; Tehila Mayzels; Elazar Raab; Mark Oskin; Yoav Etsion (IPDPS, 2018)

Inter-Thread Communication in Multithreaded, Reconfigurable Coarse-Grain Arrays. - Dani Voitsechov; Oron Port; Yoav Etsion (MICRO, 2018)

LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing. - Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel Jiménez-González; Carlos Álvarez 001; Behzad Salami 001; Sergi Madonar; Miquel Pericàs; Pedro Trancoso; et al. (SAMOS, 2018)

Inter-thread Communication in Multithreaded, Reconfigurable Coarse-grain Arrays. - Dani Voitsechov; Yoav Etsion (CoRR, 2018)

Towards Memory Prefetching with Neural Networks: Challenges and Insights. - Leeor Peled; Uri C. Weiser; Yoav Etsion (CoRR, 2018)

Efficiently Charting RDF. - Oren Kalinsky; Oren Mishali; Aidan Hogan; Yoav Etsion; Benny Kimelfeld (CoRR, 2018)

Do-It-Yourself Virtual Memory Translation. - Hanna Alam; Tianhao Zhang; Mattan Erez; Yoav Etsion (ACM SIGOPS Oper. Syst. Rev., 2018)

Using SMT to accelerate nested virtualization. - Lluís Vilanova; Nadav Amit; Yoav Etsion (ISCA, 2019)

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. - Behzad Salami 001; Konstantinos Parasyris; Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel A. Jiménez; Carlos Álvarez 001; S. Nabavi; Sergi Madonar; et al. (CoRR, 2019)

The TrieJax Architecture: Accelerating Graph Operations Through Relational Joins. - Oren Kalinsky; Benny Kimelfeld; Yoav Etsion (ASPLOS, 2020)

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. - Behzad Salami 001; Konstantinos Parasyris; Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel A. Jiménez; Carlos Álvarez 001; Seyed Saber Nabavi Larimi; Sergi Madonar; et al. (DATE, 2020)

Hardware Description Beyond Register-Transfer Level Languages. - Oron Port; Yoav Etsion (FPGA, 2020)

Semantic prefetching using forecast slices. - Leeor Peled; Uri C. Weiser; Yoav Etsion (CoRR, 2020)

A Neural Network Prefetcher for Arbitrary Memory Access Patterns. - Leeor Peled; Uri C. Weiser; Yoav Etsion (ACM Trans. Archit. Code Optim., 2020)

Exploration of Knowledge Graphs via Online Aggregation. - Oren Kalinsky; Aidan Hogan; Oren Mishali; Yoav Etsion; Benny Kimelfeld (ICDE, 2022)

DR-CGRA: Supporting Loop-Carried Dependencies in CGRAs Without Spilling Intermediate Values. - Elad Hadar; Yoav Etsion (CoRR, 2024)

Single-Address-Space FaaS with Jord. - Yuanlong Li; Atri Bhattacharyya; Madhur Kumar; Abhishek Bhattacharjee; Yoav Etsion; Babak Falsafi; Sanidhya Kashyap; Mathias Payer (ISCA, 2025)