Worst Case Analysis of DRAM Latency in Multi-requestor Systems. - Zheng Pei Wu; Yogen Krish; Rodolfo Pellizzoni (RTSS, 2013)

A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems. - Yogen Krishnapillai; Zheng Pei Wu; Rodolfo Pellizzoni (ECRTS, 2014)