A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor. - Yogesh Singh Chauhan; Costin Anghel; François Krummenacher; Renaud Gillon; Andre Baguenier; Bart Desoete; Steven Frere; Adrian Mihai Ionescu; Michel J. Declercq (ISQED, 2006)

Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications. - Dimitrios Tsamados; Yogesh Singh Chauhan; Christoph Eggimann; Adrian Mihai Ionescu (Nano-Net, 2007)

A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling. - Yogesh Singh Chauhan; François Krummenacher; Renaud Gillon; Benoit Bakeroot; Michel J. Declercq; Adrian M. Ionescu (VLSI Design, 2007)

Compact Modeling of Suspended Gate FET. - Yogesh Singh Chauhan; Dimitrios Tsamados; Nicolas Abelé; Christoph Eggimann; Michel J. Declercq; Adrian M. Ionescu (VLSI Design, 2008)

RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications. - Shyam Parthasarathy; Amit Ranjan Trivedi; Saurabh Sirohi; Robert A. Groves; Michael Olsen; Yogesh Singh Chauhan; Michael Carroll; Dan Kerr; Ali Tombak; Phil Mason (VLSI Design, 2010)

Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology. - Maria-Anna Chalkiadaki; Anurag Mangla; Christian C. Enz; Yogesh Singh Chauhan; Mohammed Ahosan Ul Karim; Sriramkumar Venugopalan; Ali M. Niknejad; Chenming Hu (ESSCIRC, 2012)

BSIM - Industry standard compact MOSFET models. - Yogesh Singh Chauhan; Sriramkumar Venugopalan; Mohammed A. Karim; Sourabh Khandelwal; Navid Paydavosi; Pankaj Thakur; Ali M. Niknejad; Chenming Hu (ESSCIRC, 2012)

BSIM compact MOSFET models for SPICE simulation. - Yogesh Singh Chauhan; Sriramkumar Venugopalan; Navid Paydavosi; Pragya Kushwaha; Srivatsava Jandhyala; Juan Pablo Duarte; Shantanu Agnihotri; Chandan Yadav; Harshit Agarwal; Ali M. Niknejad; Chenming Calvin Hu (MIXDES, 2013)

BSIM - SPICE Models Enable FinFET and UTB IC Designs. - Navid Paydavosi; Sriramkumar Venugopalan; Yogesh Singh Chauhan; Juan Pablo Duarte; Srivatsava Jandhyala; Ali M. Niknejad; Chenming Hu (IEEE Access, 2013)

BSIM6 - Benchmarking the Next-Generation MOSFET Model for RF Applications. - Anupam Dutta; Saurabh Sirohi; Ethirajan Tamilmani; Harshit Agarwal; Yogesh Singh Chauhan; Richard Q. Williams (VLSID, 2014)

BSIM-CMG: Standard FinFET compact model for advanced circuit design. - Juan Pablo Duarte; Sourabh Khandelwal; Aditya Sankar Medury; Chenming Hu; Pragya Kushwaha; Harshit Agarwal; Avirup Dasgupta; Yogesh Singh Chauhan (ESSCIRC, 2015)

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations. - Sourabh Khandelwal; Harshit Agarwal; Juan Pablo Duarte; Kaiman Chan; Sagnik Dey; Yogesh Singh Chauhan; Chenming Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach. - Girish Pahwa; Tapas Dutta; Amit Agarwal 007; Yogesh Singh Chauhan (ESSCIRC, 2016)

Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor. - Chandan Yadav; Amit Agarwal 007; Yogesh Singh Chauhan (VLSID, 2016)

Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence. - Chandan Yadav; Anupam Dutta; Saurabh Sirohi; Ethirajan Tamilmani; Yogesh Singh Chauhan (VLSID, 2016)

Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG. - Pragya Kushwaha; K. Bala Krishna; Harshit Agarwal; Sourabh Khandelwal; Juan Pablo Duarte; Chenming Hu; Yogesh Singh Chauhan (Microelectron. J., 2016)

Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs. - Avirup Dasgupta; Chetan Gupta; Anupam Dutta; Yen-Kai Lin; Srikanth Srihari; Ethirajan Tamilmani; Chenming Hu; Yogesh Singh Chauhan (VLSID, 2017)

Non-Linear RF Modeling of GaN HEMTs with Industry Standard ASM GaN Model (Invited). - Sourabh Khandelwal; Yogesh Singh Chauhan; Jason Hodges; Sayed Ali Albahrani (BCICTS, 2018)

Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance. - Hussam Amrouch; Girish Pahwa; Amol D. Gaidhane; Jörg Henkel; Yogesh Singh Chauhan (IEEE Access, 2018)

BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design. - Chetan Gupta; Ravi Goel; Harshit Agarwal; Chenming Hu; Yogesh Singh Chauhan (CICC, 2019)

Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores. - Martin Rapp; Sami Salamin; Hussam Amrouch; Girish Pahwa; Yogesh Singh Chauhan; Jörg Henkel (DAC, 2019)

NCFET-Aware Voltage Scaling. - Sami Salamin; Martin Rapp; Hussam Amrouch; Girish Pahwa; Yogesh Singh Chauhan; Jörg Henkel (ISLPED, 2019)

Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications. - Dinesh Rajasekharan; Amit Ranjan Trivedi; Yogesh Singh Chauhan (VLSID, 2019)

NCFET to Rescue Technology Scaling: Opportunities and Challenges. - Hussam Amrouch; Victor M. van Santen; Girish Pahwa; Yogesh Singh Chauhan; Jörg Henkel (ASP-DAC, 2020)

Cell Library Characterization using Machine Learning for Design Technology Co-Optimization. - Florian Klemme; Yogesh Singh Chauhan; Jörg Henkel; Hussam Amrouch (ICCAD, 2020)

Impact of Radiation on Negative Capacitance FinFET. - Govind Bajpai; Aniket Gupta; Om Prakash 007; Girish Pahwa; Jörg Henkel; Yogesh Singh Chauhan; Hussam Amrouch (IRPS, 2020)

Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET). - Johann Knechtel; Satwik Patnaik; Mohammed Nabeel 001; Mohammed Ashraf; Yogesh Singh Chauhan; Jörg Henkel; Ozgur Sinanoglu; Hussam Amrouch (CoRR, 2020)

Power Side-Channel Attacks in Negative Capacitance Transistor. - Johann Knechtel; Satwik Patnaik; Mohammed Nabeel 001; Mohammed Ashraf; Yogesh Singh Chauhan; Jörg Henkel; Ozgur Sinanoglu; Hussam Amrouch (IEEE Micro, 2020)

Associative processing using negative capacitance FDSOI transistor for pattern recognition. - Dinesh Rajasekharan; Pragya Kushwaha; Yogesh Singh Chauhan (Microelectron. J., 2020)

Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology. - Hussam Amrouch; Girish Pahwa; Amol D. Gaidhane; Chetan K. Dabhi; Florian Klemme; Om Prakash 007; Yogesh Singh Chauhan (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Transistor Self-Heating: The Rising Challenge for Semiconductor Testing. - Om Prakash 007; Chetan K. Dabhi; Yogesh Singh Chauhan; Hussam Amrouch (VTS, 2021)

A Low Noise Power Amplifier MMIC to Mitigate Co-Site Interference in 5G Front End Modules. - Neha Bajpai; Ahtisham Pampori; Paramita Maity; Manish Shah; Amitava Das; Yogesh Singh Chauhan (IEEE Access, 2021)

Impact of NCFET on Neural Network Accelerators. - Georgios Zervakis 001; Iraklis Anagnostopoulos; Sami Salamin; Yogesh Singh Chauhan; Jörg Henkel; Hussam Amrouch (IEEE Access, 2021)

Study of multi-domain switching dynamics in negative capacitance FET using SPICE model. - Amol D. Gaidhane; Amit Verma 006; Yogesh Singh Chauhan (Microelectron. J., 2021)

Improved modeling of flicker noise including velocity saturation effect in FinFETs and experimental validation. - Ravi Goel; Weike Wang; Yogesh Singh Chauhan (Microelectron. J., 2021)

On the Resiliency of NCFET Circuits Against Voltage Over-Scaling. - Guilherme Paim; Georgios Zervakis 001; Girish Pahwa; Yogesh Singh Chauhan; Eduardo Antonio Cesar da Costa; Sergio Bampi; Jörg Henkel; Hussam Amrouch (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

PROTON: Post-Synthesis Ferroelectric Thickness Optimization for NCFET Circuits. - Sami Salamin; Georgios Zervakis 001; Yogesh Singh Chauhan; Jörg Henkel; Hussam Amrouch (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A width-scalable SPICE compact model for GaN HEMTs including self-heating effect. - Raghvendra Dangi; Ahtisham Pampori; Pragya Kushwaha; Ekta Yadav; Santanu Sinha; Yogesh Singh Chauhan (DRC, 2022)

Impact of Corner Rounding on Quantum Confinement in GAA Nanosheet FETs for Advanced Technology Nodes. - Anirban Kar; Swapna Sarker; Avirup Dasgupta; Yogesh Singh Chauhan (DRC, 2022)

Self-Heating characterization and modeling of 5nm technology node FinFETs. - Shivendra Singh Parihar; Jun Z. Huang; Weike Wang; Kimihiko Imura; Yogesh Singh Chauhan (DRC, 2022)

Novel FDSOI-based Dynamic XNOR Logic for Ultra-Dense Highly-Efficient Computing. - Shubham Kumar; Swetaki Chatterjee; Chetan Kumar Dabhi; Hussam Amrouch; Yogesh Singh Chauhan (ISCAS, 2022)

A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology. - Shubham Kumar; Swetaki Chatterjee; Chetan K. Dabhi; Hussam Amrouch; Yogesh Singh Chauhan (NEWCAS, 2022)

A GaN Based Reverse Recovery Time Limiter Circuit Integrated with a Low Noise Amplifier. - Neha Bajpai; Yogesh Singh Chauhan (VDAT, 2022)

Cross-layer FeFET Reliability Modeling for Robust Hyperdimensional Computing. - Shubham Kumar; Swetaki Chatterjee; Simon Thomann; Paul R. Genssler; Yogesh Singh Chauhan; Hussam Amrouch (VLSI-SoC, 2022)

Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window. - Zhouhang Jiang; Yi Xiao 008; Swetaki Chatterjee; Halid Mulaosmanovic; Stefan Dünkel; Steven Soss; Sven Beyer; Rajiv V. Joshi; Yogesh Singh Chauhan; Hussam Amrouch; Vijaykrishnan Narayanan; Kai Ni 004 (VLSI Technology and Circuits, 2022)

Analytical approximation of surface potential and analysis of C-V characteristics of bulk MOSFETs at cryogenic temperatures. - Wajid Manzoor; Aloke K. Dutta; Yogesh Singh Chauhan (Microelectron. J., 2022)

Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU. - Sami Salamin; Georgios Zervakis 001; Florian Klemme; Hammam Kattan; Yogesh Singh Chauhan; Jörg Henkel; Hussam Amrouch (IEEE Trans. Computers, 2022)

Ferroelectric FET-Based Implementation of FitzHugh-Nagumo Neuron Model. - Dinesh Rajasekharan; Amol D. Gaidhane; Amit Ranjan Trivedi; Yogesh Singh Chauhan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Design Automation for Cryogenic CMOS Circuits. - Victor M. van Santen; Marcel Walter; Florian Klemme; Shivendra Singh Parihar; Girish Pahwa; Yogesh Singh Chauhan; Robert Wille; Hussam Amrouch (DAC, 2023)

5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing. - Shivendra Singh Parihar; Simon Thomann; Girish Pahwa; Yogesh Singh Chauhan; Hussam Amrouch (DRC, 2023)

Invited Paper: Ultra-Efficient Edge AI Using FeFET-based Monolithic 3D Integration. - Shubham Kumar; Yogesh Singh Chauhan; Hussam Amrouch (ICCAD, 2023)

Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration. - Shubham Kumar; Paul R. Genssler; Somaya Mansour; Yogesh Singh Chauhan; Hussam Amrouch (VLSI-SoC, 2023)

Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs. - Liu Liu; Shubham Kumar; Simon Thomann; Yogesh Singh Chauhan; Hussam Amrouch; Xiaobo Sharon Hu (CoRR, 2023)

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET. - Zijian Zhao 001; Shan Deng; Swetaki Chatterjee; Zhouhang Jiang; Muhammad Shaffatul Islam; Yi Xiao 008; Yixin Xu 001; Scott Meninger; Mohamed Mohamed 011; Rajiv V. Joshi; Yogesh Singh Chauhan; Halid Mulaosmanovic; et al. (CoRR, 2023)

Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs. - Shivendra Singh Parihar; Simon Thomann; Girish Pahwa; Yogesh Singh Chauhan; Hussam Amrouch (IEEE Open J. Circuits Syst., 2023)

Robust Compact Model of High-Voltage MOSFET's Drift Region. - Girish Pahwa; Ayushi Sharma; Ravi Goel; Garima Gill; Harshit Agarwal; Yogesh Singh Chauhan; Chenming Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K. - Shivendra Singh Parihar; Victor M. van Santen; Simon Thomann; Girish Pahwa; Yogesh Singh Chauhan; Hussam Amrouch (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

FerroCoin: Ferroelectric Tunnel Junction-Based True Random Number Generator. - Swetaki Chatterjee; Nikhil Rangarajan; Satwik Patnaik; Dinesh Rajasekharan; Ozgur Sinanoglu; Yogesh Singh Chauhan (IEEE Trans. Emerg. Top. Comput., 2023)

An Ultra-Low Noise Figure and Multi-Band Re-Configurable Low Noise Amplifier. - Neha Bajpai; Paramita Maity; Manish Shah; Amitava Das; Yogesh Singh Chauhan (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Computationally Efficient Compact Model for Ferroelectric Switching With Asymmetric Nonperiodic Input Signals. - Amol D. Gaidhane; Raghvendra Dangi; Shubham Sahay; Amit Verma 006; Yogesh Singh Chauhan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction. - Shubham Kumar; Swetaki Chatterjee; Simon Thomann; Yogesh Singh Chauhan; Hussam Amrouch (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

SCANet: Securing the Weights With Superparamagnetic-MTJ Crossbar Array Networks. - Dinesh Rajasekharan; Nikhil Rangarajan; Satwik Patnaik; Ozgur Sinanoglu; Yogesh Singh Chauhan (IEEE Trans. Neural Networks Learn. Syst., 2023)

Innovations in Hardware Security: Leveraging FeFET Technology for Future Opportunities. - Anirban Kar; Yogesh Singh Chauhan; Hussam Amrouch (APCCAS, 2024)

On the Severity of Self-Heating in FDSOI at Cryogenic Temperatures: In-depth Analysis from Transistors to Full Processor. - Anirban Kar; Florian Klemme; Yogesh Singh Chauhan; Hussam Amrouch (IRPS, 2024)

Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction. - Shivendra Singh Parihar; Girish Pahwa; Yogesh Singh Chauhan; Hussam Amrouch (IRPS, 2024)

Technology Mapping for Cryogenic CMOS Circuits. - Benjamin Hien; Marcel Walter; Victor M. van Santen; Florian Klemme; Shivendra Singh Parihar; Girish Pahwa; Yogesh Singh Chauhan; Hussam Amrouch; Robert Wille (ISVLSI, 2024)

Enhancing the Capabilities of Quantum Transport Simulations Utilizing Machine Learning Strategies. - Ateeb Naseer; Yawar Hayat Zarkob; Musaib Rafiq; Mohammad Sajid Nazir; Owais Ahmad; Amit Agarwal 007; Somnath Bhowmick; Yogesh Singh Chauhan (MLCAD, 2024)

Optimizing Low Noise Amplifiers: A Two-Stage Approach for Improved Noise Figure and Stability. - Mohammad Zaid; Purnima Kumari; Ahtisham Pampori; Mohammad Sajid Nazir; Umakant Goyal; Meena Mishra; Yogesh Singh Chauhan (IEEE Access, 2024)

Energy-Efficient Cryogenic Ternary Content Addressable Memory using Ferroelectric SQUID. - Shamiul Alam; Simon Thomann; Shivendra Singh Parihar; Yogesh Singh Chauhan; Kai Ni 004; Hussam Amrouch; Ahmedullah Aziz (CoRR, 2024)

Design and experimental validation of class-F-1 GaN power amplifier using a compact harmonic control unit. - Mohammad Zaid; Mohammad Sajid Nazir; Raghavendra Dangi; Yogesh Singh Chauhan (Microelectron. J., 2024)

GaN-based wide-band high-efficiency power amplifier with multi harmonic resonance. - Mohammad Zaid; Ahtisham Pampori; Mohammad Sajid Nazir; Yogesh Singh Chauhan (Microelectron. J., 2024)

Thermal Effects on Monolithic 3D Ferroelectric Transistors for Deep Neural Networks Performance. - Shubham Kumar; Yogesh Singh Chauhan; Hussam Amrouch (Adv. Intell. Syst., 2024)

Pushing the Boundaries of AI Chips: From Monolithic 3D CMOS to Cryogenic Computing. - Mahdi Benkhelifa; Shivendra Singh Parihar; Anirban Kar; Girish Pahwa; Yogesh Singh Chauhan; Hussam Amrouch (DATE, 2025)

Benchmarking Cryogenic Circuits using 5 nm FinFETs for Quantum Processing. - Anirban Kar; Shivendra Singh Parihar; Florian Klemme; Yogesh Singh Chauhan; Hussam Amrouch (ISCAS, 2025)

Ferroelectric FET-Based Bayesian Inference Engine for Disease Diagnosis. - Arka Chakraborty; Musaib Rafiq; Yawar Hayat Zarkob; Yogesh Singh Chauhan; Shubham Sahay (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Cryo-CACTI: Cryogenic-Aware CACTI for Cache Modeling Down to 10K in Advanced 7nm FinFETs. - Divya Praneetha Ravipati; Victor M. van Santen; Shivendra Singh Parihar; Yogesh Singh Chauhan; Preeti Ranjan Panda; Hussam Amrouch (IEEE Trans. Computers, 2025)