Improving CDR Performance via Estimation. - Haechang Lee; Akash Bansal; Yohan Frans; Jared Zerbe; Stefanos Sidiropoulos; Mark Horowitz (ISSCC, 2006)

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR. - Brian S. Leibowitz; Jade Kizer; Haechang Lee; Fred Chen; Andrew Ho; Metha Jeeradit; Akash Bansal; Trey Greer; Simon Li; Ramin Farjad-Rad; William F. Stonecypher; Yohan Frans; et al. (ISSCC, 2007)

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. - Haechang Lee; Kun-Yung Ken Chang; Jung-Hoon Chun; Ting Wu 003; Yohan Frans; Brian S. Leibowitz; Nhat Nguyen; T. J. Chin; Kambiz Kaviani; Jie Shen 010; Xudong Shi 004; Wendemagegnehu T. Beyene; et al. (IEEE J. Solid State Circuits, 2009)

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling. - Brian S. Leibowitz; Robert Palmer; John Poulton; Yohan Frans; Simon Li; John M. Wilson 002; Michael Bucher; Andrew M. Fuller; John G. Eyles; Marko Aleksic; Trey Greer; Nhat Nguyen (IEEE J. Solid State Circuits, 2010)

Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS. - Jafar Savoj; Hesam Amir Aslanzadeh; Declan Carey; Marc Erett; Wayne Fang; Yohan Frans; Kenny C.-H. Hsieh; Jay Im; Anup P. Jose; Didem Turker; Parag Upadhyaya; Zhaoyin Daniel Wu; et al. (CICC, 2014)

3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS. - Parag Upadhyaya; Jafar Savoj; Fu-Tai An; Ade Bekele; Anup P. Jose; Bruce Xu; Zhaoyin Daniel Wu; Didem Turker; Hesam Amir Aslanzadeh; Hiva Hedayati; Jay Im; Siok-Wei Lim; et al. (ISSCC, 2015)

A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS. - Yohan Frans; Declan Carey; Marc Erett; Hesam Amir Aslanzadeh; Wayne Y. Fang; Didem Turker; Anup P. Jose; Adebabay Bekele; Jay Im; Parag Upadhyaya; Zhaoyin Daniel Wu; Kenny C.-H. Hsieh; et al. (IEEE J. Solid State Circuits, 2015)

A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS. - Kok Lim Chan; Kee Hian Tan; Yohan Frans; Jay Im; Parag Upadhyaya; Siok-Wei Lim; Arianne Roldan; Nakul Narang; Chin Yang Koay; Hongyuan Zhao; Ken Chang (A-SSCC, 2016)

A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET. - Marc Erett; James Hudner; Declan Carey; Ronan Casey; Kevin Geary; Kay Hearne; Pedro Neto 001; Thomas Mallard; Vikas Sooden; Mark Smyth; Yohan Frans; Jay Im; et al. (ESSCIRC, 2016)

3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET. - Yohan Frans; Scott McLeod; Hiva Hedayati; Mohamed Elzeftawi; Jin Namkoong; Winson Lin; Jay Im; Parag Upadhyaya; Ken Chang (ISSCC, 2016)

A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. - Yohan Frans; Mohamed Elzeftawi; Hiva Hedayati; Jay Im; Vassili Kireev; Toan Pham; Jaewook Shin; Parag Upadhyaya; Lei Zhou; Santiago Asuncion; Chris Borrelli; Geoff Zhang; et al. (VLSI Circuits, 2016)

A 7-to-18.3GHz compact transformer based VCO in 16nm FinFET. - Mayank Raj; Parag Upadhyaya; Yohan Frans; Ken Chang (VLSI Circuits, 2016)

A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology. - Parag Upadhyaya; Ade Bekele; Didem Turker Melek; Haibing Zhao; Jay Im; Junho Cho; Kee Hian Tan; Scott McLeod; Stanley Chen; Wenfeng Zhang; Yohan Frans; Ken Chang (VLSI Circuits, 2016)

A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET. - Yohan Frans; Scott McLeod; Hiva Hedayati; Mohamed Elzeftawi; Jin Namkoong; Winson Lin; Jay Im; Parag Upadhyaya; Ken Chang (IEEE J. Solid State Circuits, 2016)

F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond. - Yohan Frans; Ichiro Fujimori; Seung-Jun Bae; Samuel Palermo; Hideyuki Nosaka; Simone Erba (ISSCC, 2017)

6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET. - Jay Im; Dave Freitas; Arianne Roldan; Ronan Casey; Stanley Chen; Adam Chou; Tim Cronin; Kevin Geary; Scott McLeod; Lei Zhou; Ian Zhuang; Jaeduk Han; et al. (ISSCC, 2017)

A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS. - Kok Lim Chan; Kee Hian Tan; Yohan Frans; Jay Im; Parag Upadhyaya; Siok-Wei Lim; Arianne Roldan; Nakul Narang; Chin Yang Koay; Hongyuan Zhao; Ping-Chuan Chiang; Ken Chang (IEEE J. Solid State Circuits, 2017)

A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET. - Marc Erett; James Hudner; Declan Carey; Ronan Casey; Kevin Geary; Kay Hearne; Pedro Neto 001; Thomas Mallard; Vikas Sooden; Mark Smyth; Yohan Frans; Jay Im; et al. (IEEE J. Solid State Circuits, 2017)

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET. - Yohan Frans; Jaewook Shin; Lei Zhou; Parag Upadhyaya; Jay Im; Vassili Kireev; Mohamed Elzeftawi; Hiva Hedayati; Toan Pham; Santiago Asuncion; Chris Borrelli; Geoff Zhang; et al. (IEEE J. Solid State Circuits, 2017)

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET. - Jay Im; Dave Freitas; Arianne Roldan; Ronan Casey; Stanley Chen; Adam Chou; Tim Cronin; Kevin Geary; Scott McLeod; Lei Zhou; Ian Zhuang; Jaeduk Han; et al. (IEEE J. Solid State Circuits, 2017)

A 56 Gb/s 6 mW 300 um2 inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS. - Kevin Zheng; Yohan Frans; Ken Chang; Boris Murmann (CICC, 2018)

A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET. - Stanley Chen; Lei Zhou; Ian Zhuang; Jay Im; Didem Turker Melek; Jinyung Namkoong; Mayank Raj; Jaewook Shin; Yohan Frans; Ken Chang (ISSCC, 2018)

A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET. - Marc Erett; Declan Carey; James Hudner; Ronan Casey; Kevin Geary; Pedro Neto 001; Mayank Raj; Scott McLeod; Hongtao Zhang 002; Arianne Roldan; Hongyuan Zhao; Ping-Chuan Chiang; et al. (ISSCC, 2018)

A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs. - Didem Turker; Ade Bekele; Parag Upadhyaya; Bob Verbruggen; Ying Cao 010; Shaojun Ma; Christophe Erdmann; Brendan Farley; Yohan Frans; Ken Chang (ISSCC, 2018)

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET. - Parag Upadhyaya; Chi Fung Poon; Siok-Wei Lim; Junho Cho; Arianne Roldan; Wenfeng Zhang; Jin Namkoong; Toan Pham; Bruce Xu; Winson Lin; Hongtao Zhang 002; Nakul Narang; et al. (ISSCC, 2018)

A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. - James Hudner; Declan Carey; Ronan Casey; Kay Hearne; Pedro Wilson de Abreu Farias Neto; Ilias Chlis; Marc Erett; Chi Fung Poon; Asma Laraba; Hongtao Zhang 002; Sai Lalith Chaitanya Ambatipudi; David Mahashin; et al. (VLSI Circuits, 2018)

A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET. - Jay Im; Stanley Chen; Dave Freitas; Adam Chou; Lei Zhou; Ian Zhuang; Tim Cronin; David Mahashin; Winson Lin; Kok Lim Chan; Hongyuan Zhao; Kee Hian Tan; et al. (VLSI Circuits, 2018)

A 112-GB/S PAM4 Transmitter in 16NM FinFET. - Kee Hian Tan; Ping-Chuan Chiang; Yipeng Wang 003; Haibing Zhao; Arianne Roldan; Hongyuan Zhao; Nakul Narang; Siok-Wei Lim; Declan Carey; Sai Lalith Chaitanya Ambatipudi; Parag Upadhyaya; Yohan Frans; et al. (VLSI Circuits, 2018)

An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS. - Kevin Zheng; Yohan Frans; Sai Lalith Ambatipudi; Santiago Asuncion; Hari Teja Reddy; Ken Chang; Boris Murmann (VLSI Circuits, 2018)

A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET. - Marc Erett; Declan Carey; Ronan Casey; James Hudner; Kevin Geary; Ted Lee; Mayank Raj; Hongtao Zhang 002; Arianne Roldan; Hongyuan Zhao; Ping-Chuan Chiang; Haibing Zhao; et al. (CICC, 2019)

ADC-based Wireline Transceiver. - Yohan Frans (CICC, 2019)

A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. - Mayank Raj; Yohan Frans; Sai Lalith Chaitanya Ambatipudi; David Mahashin; Peter De Heyn; Sadhishkumar Balakrishnan; Joris Van Campenhout; Jimmy Grayson; Marc Epitaux; Ken Chang (VLSI Circuits, 2019)

Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC). - Yohan Frans; Wim Dehaene; Masato Motomura; Seung-Jun Bae (IEEE J. Solid State Circuits, 2019)

A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET. - Parag Upadhyaya; Chi Fung Poon; Siok-Wei Lim; Junho Cho; Arianne Roldan; Wenfeng Zhang; Jin Namkoong; Toan Pham; Bruce Xu; Winson Lin; Hongtao Zhang 002; Nakul Narang; et al. (IEEE J. Solid State Circuits, 2019)

50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. - Mayank Raj; Yohan Frans; Ping-Chuan Chiang; Sai Lalith Chaitanya Ambatipudi; David Mahashin; Peter De Heyn; Sadhishkumar Balakrishnan; Joris Van Campenhout; Jimmy Grayson; Marc Epitaux; Ken Chang (ECOC, 2020)

Xilinx Versal™ Premium. - Martin Voogel; Yohan Frans; Matt Ouellette; Jason Coppens; Sagheer Ahmad; Jaideep Dastidar; Ehab Mohsen; Faisal Dada; Mike Thompson; Ralph Wittig; Trevor Bauer; Gaurav Singh (Hot Chips Symposium, 2020)

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. - Jay Im; Kevin Zheng; Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (ISSCC, 2020)

Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET. - Mayank Raj; Yohan Frans; Ping-Chuan Chiang; Sai Lalith Chaitanya Ambatipudi; David Mahashin; Peter De Heyn; Sadhishkumar Balakrishnan; Joris Van Campenhout; Jimmy Grayson; Marc Epitaux; Ken Chang (IEEE J. Solid State Circuits, 2020)

F6: Optical and Electrical Transceivers for 400GbE and Beyond. - Tony Chan Carusone; Sudip Shekhar; Yohan Frans; Wei-Zen Chen; Thomas Toifl; Munehiko Nagatani; Franz Dielacher; William Redman-White (ISSCC, 2021)

Session 8 Overview: Ultra-High-Speed Wireline Wireline Subcommittee. - Yohan Frans; Patrick Yue; Thomas Toifl (ISSCC, 2021)

A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET. - Chi Fung Poon; Wenfeng Zhang; Junho Cho; Shaojun Ma; Yipeng Wang 003; Ying Cao 010; Asma Laraba; Eugene Ho; Winson Lin; Zhaoyin Daniel Wu; Kee Hian Tan; Parag Upadhyaya; et al. (VLSI Circuits, 2021)

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. - Jay Im; Kevin Zheng; Chuen-Huei Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (IEEE J. Solid State Circuits, 2021)

A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET. - Chi Fung Poon; Wenfeng Zhang; Junho Cho; Shaojun Ma; Yipeng Wang 003; Ying Cao 010; Asma Laraba; Eugene Ho; Winson Lin; Zhaoyin Daniel Wu; Kee Hian Tan; Parag Upadhyaya; et al. (IEEE J. Solid State Circuits, 2022)

A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies. - Mayank Raj; Chuan Xie; Ade Bekele; Adam Chou; Wenfeng Zhang; Ying Cao 010; Jae Wook Kim; Nakul Narang; Hongyuan Zhao; Yipeng Wang 003; Kee Hian Tan; Winson Lin; et al. (ISSCC, 2023)

A 64 Gb/s NRZ O-Band Ring Modulator with 3.2 THz FSR for DWDM Applications. - Chuan Xie; Mayank Raj; Anish Joshi; Zakriya Mohammed; Gareeyasee Saha; Zhaowen Wang; Parag Upadhyaya; Yohan Frans (OFC, 2024)

Adaptive Wavelength Tracking and Temperature Tuning of A 45Gbps Coupled Ring Resonator Based DWDM Link. - Zhaowen Wang; Ade Bekele; Mingshan Li; Mayank Raj; Chuan Xie; Anish Joshi; Gareeyasee Saha; Zakriya Mohammed; Stuart Daudlin; Parag Upadhyaya; Yohan Frans (OFC, 2025)