A Shogi Processor with a Field Programmable Gate Array. - Yohei Hori; Minenobu Seki; Reijer Grimbergen; Tsutomu Maruyama; Tsutomu Hoshino (Computers and Games, 2000)

An FPGA-based processor for shogi mating problems. - Yohei Hori; Masashi Sonoyama; Tsutomu Maruyama (FPT, 2002)

A tsume-shogi processor based on reconfigurable hardware. - Yohei Hori; Tsutomu Maruyama; Kenji Toda (FPT, 2004)

Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration. - Yohei Hori; Hiroyuki Yokoyama; Kenji Toda (FPL, 2006)

A Secure Digital Content Delivery System Based on Partially Reconfigurable Hardware. - Yohei Hori; Hiroyuki Yokoyama; Hirofumi Sakane; Kenji Toda (FPT, 2007)

Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. - Yohei Hori; Akashi Satoh; Hirofumi Sakane; Kenji Toda (FPL, 2008)

Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems. - Yohei Hori; Akashi Satoh; Hirofumi Sakane; Kenji Toda (IWSEC, 2008)

A Secure Content Delivery System Based on a Partially Reconfigurable FPGA. - Yohei Hori; Hiroyuki Yokoyama; Hirofumi Sakane; Kenji Toda (IEICE Trans. Inf. Syst., 2008)

Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. - Yohei Hori; Takahiro Yoshida; Toshihiro Katashita; Akashi Satoh (ReConFig, 2010)

A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. - Daisuke Fujimoto; Makoto Nagata; Toshihiro Katashita; Akihiro T. Sasaki; Yohei Hori; Akashi Satoh (HOST, 2011)

Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function. - Yohei Hori; Hyunho Kang; Toshihiro Katashita; Akashi Satoh (ReConFig, 2011)

Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA. - Yohei Hori; Toshihiro Katashita; Kazukuni Kobara (GCCE, 2013)

A novel smart card development platform for evaluating physical attacks and PUFs. - Toshihiro Katashita; Akihiko Sasaki; Yohei Hori (GCCE, 2013)

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. - Daisuke Fujimoto; Toshihiro Katashita; Akihiko Sasaki; Yohei Hori; Akashi Satoh; Makoto Nagata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption. - Yohei Hori; Toshihiro Katashita; Hirofumi Sakane; Kenji Toda; Akashi Satoh (IEICE Trans. Inf. Syst., 2013)

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. - Daisuke Fujimoto; Noriyuki Miura; Makoto Nagata; Yu-ichi Hayashi; Naofumi Homma; Takafumi Aoki; Yohei Hori; Toshihiro Katashita; Kazuo Sakiyama; Thanh-Ha Le; Julien Bringer; Pirouz Bazargan-Sabet; et al. (IEICE Trans. Electron., 2014)

Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays. - Yohei Hori; Hyunho Kang; Toshihiro Katashita; Akashi Satoh; Shin-ichi Kawamura; Kazukuni Kobara (J. Inf. Process., 2014)

Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness tests. - Yasuhiro Ogasahara; Yohei Hori; Hanpei Koike (GCCE, 2015)

Implementation of pseudo linear feedback shift register physical unclonable function on silicon. - Yasuhiro Ogasahara; Yohei Hori; Hanpei Koike (ISCAS, 2016)

Prototype of USB stick-sized PUF module for authentication and key generation. - Toshihiro Katashita; Yohei Hori; Yasuhiro Ogasahara (GCCE, 2017)

Development of the Unified Security Requirements of PUFs During the Standardization Process. - Nicolas Bruneau; Jean-Luc Danger; Adrien Facon; Sylvain Guilley; Soshi Hamaguchi; Yohei Hori; Yousung Kang; Alexander Schaub 001 (SecITC, 2018)

Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device. - Toshihiro Katashita; Masakazu Hioki; Yohei Hori; Hanpei Koike (IEICE Trans. Inf. Syst., 2018)

DeviceVeil: Robust Authentication for Individual USB Devices Using Physical Unclonable Functions. - Kuniyasu Suzaki; Yohei Hori; Kazukuni Kobara; Mohammad Mannan (DSN, 2019)

A Deep Learning Attack Countermeasure with Intentional Noise for a PUF-Based Authentication Scheme. - Risa Yashiro; Yohei Hori; Toshihiro Katashita; Kazuo Sakiyama (SECITC, 2019)

Cause Analysis Method of Entropy Loss in Physically Unclonable Functions. - Mitsuru Shiozaki; Yohei Hori; Tatsuya Oyama; Masayoshi Shirahata; Takeshi Fujino (ISCAS, 2020)

Entropy Estimation of Physically Unclonable Functions. - Mitsuru Shiozaki; Yohei Hori; Takeshi Fujino (IACR Cryptol. ePrint Arch., 2020)

Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping. - Yasuhiro Ogasahara; Yohei Hori; Toshihiro Katashita; Tomoki Iizuka; Hiromitsu Awano; Makoto Ikeda; Hanpei Koike (Integr., 2020)

Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices. - Yusuke Yano; Kengo Iokibe; Toshiaki Teshima; Yoshitaka Toyota; Toshihiro Katashita; Yohei Hori (IEICE Trans. Commun., 2021)

FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks. - Tatsuya Oyama; Mika Sakai; Yohei Hori; Toshihiro Katashita; Takeshi Fujino (ACNS Workshops (1), 2024)

Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation. - Hiroshi Fuketa; Toshihiro Katashita; Yohei Hori; Masakazu Hioki (IEEE Access, 2024)

Fully Quantized Matrix Arithmetic-Only BERT Model and Its FPGA-Based Accelerator. - Hiroshi Fuketa; Toshihiro Katashita; Yohei Hori; Masakazu Hioki (IEEE Access, 2025)