Stochastic TDC architecture with self-calibration. - Satoshi Ito; Shigeyuki Nishimura; Haruo Kobayashi 001; Satoshi Uemori; Yohei Tan; Nobukazu Takai; Takahiro J. Yamaguchi; Kiichi Niitsu (APCCAS, 2010)

SAR ADC that is configurable to optimize yield. - Tomohiko Ogawa; Haruo Kobayashi 001; Yohei Tan; Satoshi Ito; Satoshi Uemori; Nobukazu Takai; Kiichi Niitsu; Takahiro J. Yamaguchi; Tatsuji Matsuura; Nobuyoshi Ishikawa (APCCAS, 2010)

ADC linearity test signal generation algorithm. - Satoshi Uemori; Takahiro J. Yamaguchi; Satoshi Ito; Yohei Tan; Haruo Kobayashi 001; Nobukazu Takai; Kiichi Niitsu; Nobuyoshi Ishikawa (APCCAS, 2010)

Background calibration algorithm for pipelined ADC with open-loop residue amplifier using split ADC structure. - Takuya Yagi; Kunihiko Usui; Tatsuji Matsuura; Satoshi Uemori; Yohei Tan; Satoshi Ito; Haruo Kobayashi 001 (APCCAS, 2010)

Design for Testability That Reduces Linearity Testing Time of SAR ADCs. - Tomohiko Ogawa; Haruo Kobayashi 001; Satoshi Uemori; Yohei Tan; Satoshi Ito; Nobukazu Takai; Takahiro J. Yamaguchi; Kiichi Niitsu (IEICE Trans. Electron., 2011)

Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme. - Takuya Yagi; Kunihiko Usui; Tatsuji Matsuura; Satoshi Uemori; Satoshi Ito; Yohei Tan; Haruo Kobayashi 001 (IEICE Trans. Electron., 2011)