An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application. - Tohru Furuyama; Takashi Ohsawa; Yousei Nagahama; Hiroto Tanaka; Yohji Watanabe; Tohru Kimura; Kazuyoshi Muraoka; Kenji Natori (IEEE J. Solid State Circuits, 1989)

A new CR-delay circuit technology for high-density and high-speed DRAMs. - Yohji Watanabe; Takashi Ohsawa; Kiyofumi Sakurai; Tohru Furuyama (IEEE J. Solid State Circuits, 1989)

A 12 MHz data cycle 4 Mb DRAM with pipeline operation. - Natsuki Kushiyama; Yohji Watanabe; Takashi Ohsawa; Kazuyoshi Muraoka; Yousei Nagahama; Tohru Furuyama (IEEE J. Solid State Circuits, 1991)

A 33-ns 64-Mb DRAM. - Yukihito Oowaki; Kenji Tsuchida; Yohji Watanabe; Daisaburo Takashima; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Akihiro Nitayama; Fumio Horiguchi; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1991)

Word-line architecture for highly reliable 64-Mb DRAM. - Daisaburo Takashima; Yukihito Oowaki; Ryu Ogiwara; Yohji Watanabe; Kenji Tsuchida; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1992)

Offset compensating bit-line sensing scheme for high density DRAM's. - Yohji Watanabe; Nobuo Nakamura; Shigeyoshi Watanabe (IEEE J. Solid State Circuits, 1994)

Fault-tolerant designs for 256 Mb DRAM. - Toshiaki Kirihata; Yohji Watanabe; Hing Wong; John K. DeBrosse; Munehiro Yoshida; Daisuke Kato; Shuso Fujii; Matthew R. Wordeman; Peter Poechmueller; Stephen A. Parke; Yoshiaki Asao (IEEE J. Solid State Circuits, 1996)

A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. - Yohji Watanabe; Ring Wong; Toshiaki Kirihata; Daisuke Kato; John K. DeBrosse; Takahiko Rara; Munehiro Yoshida; Rideo Mukai; Khandker N. Quader; Takeshi Nagai; Peter Poechmueller; Peter Pfefferl; et al. (IEEE J. Solid State Circuits, 1996)

Flexible test mode approach for 256-Mb DRAM. - Toshiaki Kirihata; Hing Wong; John K. DeBrosse; Yohji Watanabe; Takahiko Hara; Munehiro Yoshida; Matthew R. Wordeman; Shuso Fujii; Yoshiaki Asao; Bo Krsnik (IEEE J. Solid State Circuits, 1997)

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. - Hidehiro Shiga; Daisaburo Takashima; Shinichiro Shiratake; Katsuhiko Hoya; Tadashi Miyakawa; Ryu Ogiwara; Ryo Fukuda; Ryosuke Takizawa; Kosuke Hatsuda; Fumiyoshi Matsuoka; Yasushi Nagadomi; Daisuke Hashimoto; et al. (ISSCC, 2009)

A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. - Daisaburo Takashima; Hidehiro Shiga; Daisuke Hashimoto; Tadashi Miyakawa; Shinichiro Shiratake; Katsuhiko Hoya; Ryu Ogiwara; Ryosuke Takizawa; Ryosuke Doumae; Ryo Fukuda; Yohji Watanabe; Shuso Fujii; et al. (ISSCC, 2010)

A 64Mb MRAM with clamped-reference and adequate-reference schemes. - Kenji Tsuchida; Tsuneo Inaba; Katsuyuki Fujita; Yoshihiro Ueda; Takafumi Shimizu; Yoshiaki Asao; Takeshi Kajiyama; Masayoshi Iwayama; Kuniaki Sugiura; Sumio Ikegawa; Tatsuya Kishi; Tadashi Kai; et al. (ISSCC, 2010)

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. - Hidehiro Shiga; Daisaburo Takashima; Shinichiro Shiratake; Katsuhiko Hoya; Tadashi Miyakawa; Ryu Ogiwara; Ryo Fukuda; Ryosuke Takizawa; Kosuke Hatsuda; Fumiyoshi Matsuoka; Yasushi Nagadomi; Daisuke Hashimoto; et al. (IEEE J. Solid State Circuits, 2010)

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance. - Daisaburo Takashima; Yasushi Nagadomi; Kosuke Hatsuda; Yohji Watanabe; Shuso Fujii (IEEE J. Solid State Circuits, 2011)

A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs. - Daisaburo Takashima; Hidehiro Shiga; Daisuke Hashimoto; Tadashi Miyakawa; Shinichiro Shiratake; Katsuhiko Hoya; Ryu Ogiwara; Ryosuke Takizawa; Ryosuke Doumae; Ryo Fukuda; Yohji Watanabe; Shuso Fujii; et al. (IEEE J. Solid State Circuits, 2011)

A perspective on NVRAM technology for future computing system. - Katsuhiko Hoya; Kosuke Hatsuda; Kenji Tsuchida; Yohji Watanabe; Yusuke Shirota; Tatsunori Kanai (VLSI-DAT, 2019)