Fault Tolerant Neural Networks in Optimization Problems. - Yoichi Koyanagi; Yoshihiro Tohma (FTCS, 1992)

Design of Neural Networks to Tolerate the Mixture of Two Types of Faults. - Yoshihiro Tohma; Yoichi Koyanagi (FTCS, 1993)

AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler. - Kenichi Hayashi; Tsunehisa Doi; Takeshi Horie; Yoichi Koyanagi; Osamu Shiraki; Nobutaka Imamura; Toshiyuki Shimizu; Hiroaki Ishihata; Tatsuya Shindo (ASPLOS, 1994)

Fault-Tolerant Design of Neural Networks for Solving Optimization Problems. - Yoshihiro Tohma; Yoichi Koyanagi (IEEE Trans. Computers, 1996)

Synfinity II-a high-speed interconnect with 2 GBytes/sec self-configurable physical link. - Yoichi Koyanagi; Takeshi Horie; Takashi Miyoshi; Mitsuo Ishii (Hot Interconnects, 2001)

Design Consideration of 6.25 Gbps Signaling for High-Performance Server. - Jian Hong Jiang; Weixin Gai; Akira Hattori; Yasuo Hidaka; Takeshi Horie; Yoichi Koyanagi; Hideki Osone (ASP-DAC, 2007)

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer. - Yasuo Hidaka; Weixin Gai; Akira Hattori; Takeshi Horie; Jian Jiang; Kouichi Kanda; Yoichi Koyanagi; Satoshi Matsubara; Hideki Osone (ISSCC, 2007)

A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. - Yasuo Hidaka; Weixin Gai; Takeshi Horie; Jian Hong Jiang; Yoichi Koyanagi; Hideki Osone (ISSCC, 2009)

A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control. - Yasuo Hidaka; Weixin Gai; Takeshi Horie; Jian Hong Jiang; Yoichi Koyanagi; Hideki Osone (IEEE J. Solid State Circuits, 2009)

A Single-Chip, 10-Gigabit Ethernet Switch LSI for Energy-Efficient Blade Servers. - Yukihiro Nakagawa; Takeshi Shimizu; Yoichi Koyanagi; Osamu Shiraki; Shinji Kobayashi; Kazuki Hyoudou; Takashi Miyoshi; Yuuki Ogata; Yasushi Umezawa; Takeshi Horie; Akira Hattori (GreenCom/CPSCom, 2010)

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. - Yasuo Hidaka; Takeshi Horie; Yoichi Koyanagi; Takashi Miyoshi; Hideki Osone; Samir Parikh; Subodh M. Reddy; Toshiyuki Shibuya; Yasushi Umezawa; William W. Walker (ISSCC, 2011)

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. - Yoshiyasu Doi; Takayuki Shibasaki; Takumi Danjo; Win Chaivipas; Takushi Hashida; Hiroki Miyaoka; Masanori Hoshino; Yoichi Koyanagi; Takuji Yamamoto; Sanroku Tsukamoto; Hirotaka Tamura (ISSCC, 2013)

A 10th generation 16-core SPARC64 processor for mission-critical UNIX server. - Ryuji Kan; Tomohiro Tanaka; Go Sugizaki; Ryuichi Nishiyama; Sota Sakabayashi; Yoichi Koyanagi; Ryuji Iwatsuki; Kazumi Hayasaka; Taiki Uemura; Gaku Ito; Yoshitomo Ozeki; Hiroyuki Adachi; et al. (ISSCC, 2013)

32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE. - Yuuki Ogata; Yasuo Hidaka; Yoichi Koyanagi; Sadanori Akiya; Yuji Terao; Kosuke Suzuki; Keisuke Kashiwa; Masanobu Suzuki; Hirotaka Tamura (ISSCC, 2013)

A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. - Samir Parikh; Tony Kao; Yasuo Hidaka; Jian Jiang; Asako Toda; Scott McLeod; William W. Walker; Yoichi Koyanagi; Toshiyuki Shibuya; Jun Yamada (ISSCC, 2013)

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. - Yoshiyasu Doi; Takayuki Shibasaki; Takumi Danjo; Win Chaivipas; Takushi Hashida; Hiroki Miyaoka; Masanori Hoshino; Yoichi Koyanagi; Takuji Yamamoto; Sanroku Tsukamoto; Hirotaka Tamura (IEEE J. Solid State Circuits, 2013)

A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution. - Takushi Hashida; Yasumoto Tomita; Yuuki Ogata; Kosuke Suzuki; Shigeto Suzuki; Takanori Nakao; Yuji Terao; Satofumi Honda; Sota Sakabayashi; Ryuichi Nishiyama; Akihiko Konmoto; Yoshitomo Ozeki; et al. (VLSIC, 2014)

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS. - Takayuki Shibasaki; Win Chaivipas; Yanfei Chen; Yoshiyasu Doi; Takayuki Hamada; Hideki Takauchi; Toshihiko Mori; Yoichi Koyanagi; Hirotaka Tamura (VLSIC, 2014)

The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server. - Ryuji Kan; Tomohiro Tanaka; Go Sugizaki; Kinya Ishizaka; Ryuichi Nishiyama; Sota Sakabayashi; Yoichi Koyanagi; Ryuji Iwatsuki; Kazumi Hayasaka; Taiki Uemura; Gaku Ito; Yoshitomo Ozeki; et al. (IEEE J. Solid State Circuits, 2014)

22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI. - Yanfei Chen; Masaya Kibune; Asako Toda; Akinori Hayakawa; Tomoyuki Akiyama; Shigeaki Sekiguchi; Hiroji Ebe; Nobuhiro Imaizumi; Tomoyuki Akahoshi; Suguru Akiyama; Shinsuke Tanaka; Takasi Simoyama; et al. (ISSCC, 2015)

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS. - Takayuki Shibasaki; Yukito Tsunoda; Hideki Oku; Satoshi Ide; Toshihiko Mori; Yoichi Koyanagi; Kazuhiro Tanaka; Tomohiro Ishihara; Hirotaka Tamura (ISSCC, 2015)

22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS. - Yukito Tsunoda; Takayuki Shibasaki; Satoshi Ide; Toshihiko Mori; Yoichi Koyanagi; Kazuhiro Tanaka; Tomohiro Ishihara; Hirotaka Tamura (ISSCC, 2015)

25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs. - Yukito Tsunoda; Takayuki Shibasaki; Hideki Oku; Satoshi Ide; Toshihiko Mori; Yoichi Koyanagi; Kazuhiro Tanaka; Tomohiro Ishihara; Hirotaka Tamura (OFC, 2015)

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. - Takayuki Shibasaki; Takumi Danjo; Yuuki Ogata; Yasufumi Sakai; Hiroki Miyaoka; Futoshi Terasawa; Masahiro Kudo; Hideki Kano; Atsushi Matsuda; Shigeaki Kawai; Tomoyuki Arai; Hirohito Higashi; et al. (ISSCC, 2016)

24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR. - Yukito Tsunoda; Takayuki Shibasaki; Hideki Oku; Jun Matsui; Takashi Shiraishi; Satoshi Ide; Toshihiko Mori; Yoichi Koyanagi; Hirotaka Tamura (OFC, 2016)

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. - Hiroki Miyaoka; Futoshi Terasawa; Masahiro Kudo; Hideki Kano; Atsushi Matsuda; Noriaki Shirai; Shigeaki Kawai; Takayuki Shibasaki; Takumi Danjo; Yuuki Ogata; Yasufumi Sakai; Hisakatsu Yamaguchi; et al. (VLSI Circuits, 2016)