A 400 K-transistor CMOS sea-of-gates array with continuous track allocation. - Masatomi Okabe; Yoshihiro Okuno; Takahiko Arakawa; Ichiro Tomioka; Takio Ohno; Tomoyoshi Noda; Masahiro Hatanaka; Yoichi Kuramitsu (IEEE J. Solid State Circuits, 1989)

Design for reducing alpha-particle-induced soft errors in ECL logic circuitry. - Masatomi Okabe; Makoto Tatsuki; Yutaka Arima; Tadashi Hirao; Yoichi Kuramitsu (IEEE J. Solid State Circuits, 1989)

A 209 K-transistor ECL gate array with RAM. - Hisayasu Sato; Takashi Nishimura; Makoto Tatsuki; Atsushi Ohba; Shiro Hine; Yoichi Kuramitsu (IEEE J. Solid State Circuits, 1989)