A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design. - Kenichi Imamiya; Jun-ichi Miyamoto; Shigeru Atsumi; Nobuaki Ohtsuka; Yukinori Muroya; Toshiyuki Sako; Masao Higashino; Yumiko Iyama; Seiichi Mori; Yoichi Ohshima; Hitoshi Araki; Yukio Kaneko; et al. (IEEE J. Solid State Circuits, 1990)

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique. - Naoto Tomita; Nobuaki Ohtsuka; Jun-ichi Miyamoto; Ken-ichi Imamiya; Yumiko Iyama; Seiichi Mori; Yoichi Ohshima; Norihisa Arai; Yukio Kaneko; Eiji Sakagami; Kuniyoshi Yoshikawa; Sumio Tanaka (IEEE J. Solid State Circuits, 1991)

A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation. - Shigeru Atsumi; Masao Kuriyama; Akira Umezawa; Hironori Banba; Kiyomi Naruke; Seiji Yamada; Yoichi Ohshima; Masamitsu Oshikiri; Yohei Hiura; Tomoko Yamane; Kuniyoshi Yoshikawa (IEEE J. Solid State Circuits, 1994)