An SoC architecture and its design methodology using unifunctional heterogeneous processor array. - Yoichi Yuyama; Masao Aramoto; Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2004)

RTL/ISS co-modeling methodology for embedded processor using SystemC. - Yoichi Yuyama; Masao Aramoto; Kazutoshi Kobayashi; Hidetoshi Onodera (ISCAS (5), 2004)

A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. - Kazutoshi Kobayashi; Masao Aramoto; Yoichi Yuyama; Akihiko Higuchi; Hidetoshi Onodera (ASP-DAC, 2005)

Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect. - Yoichi Yuyama; Akira Tsuchiya; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2006)

A 45nm 37.3GOPS/W heterogeneous multi-core SoC. - Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Shigezumi Matsui; Osamu Nishii; Atsushi Hasegawa; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Koichi Terada; Tohru Nojiri; et al. (ISSCC, 2010)

Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU. - Minh Thien Trieu; Huong Thien Hoang; Phong The Vo; Hung Bao Vo; Yoichi Yuyama (ASICON, 2011)

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. - Osamu Nishii; Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Yasutaka Wada; Keiji Kimura; Hironori Kasahara; Hideo Maejima (IEICE Trans. Electron., 2011)