TITAC: Design of A Quasi-Delay-Insensitive Microprocessor. - Takashi Nanya; Yoichiro Ueno; Hiroto Kagotani; Masashi Kuwako; Akihiro Takamura (IEEE Des. Test Comput., 1994)

TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. - Akihiro Takamura; Masashi Kuwako; Masashi Imai; Taro Fujii; Motokazu Ozawa; Izumi Fukasaku; Yoichiro Ueno; Takashi Nanya (ICCD, 1997)

TITAC-2: An Asynchronous 32-bit Microprocessor. - Akihiro Takamura; Motokazu Ozawa; Izumi Fukasaku; Taro Fujii; Yoichiro Ueno; Masashi Imai; Masashi Kuwako; Takashi Nanya (ASP-DAC, 1998)

Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. - Motokazu Ozawa; Masashi Imai; Hiroshi Nakamura; Takashi Nanya; Yoichiro Ueno (ASYNC, 2001)

Disaster recovery mechanism using widely distributed networking and secure metadata handling technology. - Yoichiro Ueno; Noriharu Miyaho; Shuichi Suzuki (UPGRADE-CN, 2009)

Autonomous and distributed internet security (AIS) infrastructure for safe internet. - Hiroyuki Kimiyama; Naoki Yonezaki; Tomoaki Tsutsumi; Kaori Sano; Hirofumi Yamaki; Yoichiro Ueno; Ryôichi Sasaki; Hiroshi Kobayashi (NOF, 2017)

Next Generation Connectionless IP router architecture with Switching Delay for URLLC Services. - Yoichiro Ueno; Akihiko Tsukahara; Noriharu Miyaho (HPSR, 2023)

Feasibility Study of Next-Generation Connectionless IP Router with Ultra-Low Switching Delay for URLLC Services. - Yoichiro Ueno; Akihiko Tsukahara; Noriharu Miyaho (HPSR, 2025)