The minimum width routing of A 2-row 2-layer polycell-layout. - Tatsuya Kawamoto; Yoji Kajitani (DAC, 1979)

Order of Channels for Safe Routing and Optimal Compaction of Routing Area. - Yoji Kajitani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

The channel expansion problem in layout design. - Rachel R. Chen; Yoji Kajitani (DAC, 1984)

A matroid generalization of theorems of Lewin and Gallai. - Yoji Kajitani; Shuichi Ueno (Discret. Appl. Math., 1984)

Characterization of partial 3-trees in terms of three structures. - Yoji Kajitani; Akio Ishizuka; Shuichi Ueno (Graphs Comb., 1986)

The minimum augmentation of a directed tree to a k-edge-connected directed graph. - Yoji Kajitani; Shuichi Ueno (Networks, 1986)

Ordering of the elements of a matroid such that its consecutive w elements are independent. - Yoji Kajitani; Shuichi Ueno; Hiroshi Miyano (Discret. Math., 1988)

On the nonseparating independent set problem and feedback set problem for graphs with no vertex degree exceeding three. - Shuichi Ueno; Yoji Kajitani; Shin'ya Gotoh (Discret. Math., 1988)

Minimum augmentation of a tree to a K-edge-connected graph. - Shuichi Ueno; Yoji Kajitani; Hajime Wada (Networks, 1988)

Mixed-Searching and Proper-Path-Width. - Atsushi Takahashi 001; Shuichi Ueno; Yoji Kajitani (ISA, 1991)

Peel-the-box: a concept of switch-box routing and tractable problems. - Atsushi Takahashi 001; Yoji Kajitani (Integr., 1992)

The Virtual Dimensions of a Straight Line Embedding of a plane Graph. - Toshihiko Takahashi; Yoji Kajitani (Algorithmic Aspects of VLSI Layout, 1993)

Optimal single hop multiple bus networks. - Wayne Wei-Ming Dai; Yoji Kajitani; Yorihiko Hirata (ISCAS, 1993)

Generalization of aTheorem on the Parametric Maximum Flow Problem. - Tadashi Arai; Shuichi Ueno; Yoji Kajitani (Discret. Appl. Math., 1993)

Channel-driven global routing with consistent placement (extended abstract). - Shigetoshi Nakatake; Yoji Kajitani (ICCAD, 1994)

The Totally-Perfect Bipartite Graph and Its Construction. - Kunihiro Fujiyoshi; Yoji Kajitani; Hiroshi Niitsu (ISAAC, 1994)

Design of Optimum Totally Perfect Connection-Blocks of FPGA. - Kunihiro Fujiyoshi; Yoji Kajitani; Hiroshi Niitsu (ISCAS, 1994)

New Approximation Results on Graph Matching and related Problems. - Yoji Kajitani; Jun Dong Cho; Majid Sarrafzadeh (WG, 1994)

Minimal acyclic forbidden minors for the family of graphs with bounded path-width. - Atsushi Takahashi 001; Shuichi Ueno; Yoji Kajitani (Discret. Math., 1994)

Rectangle-packing-based module placement. - Hiroshi Murata; Kunihiro Fujiyoshi; Shigetoshi Nakatake; Yoji Kajitani (ICCAD, 1995)

Detailed-Routability of FPGAs with Extremal Switch-Block Structures. - Yasuhiro Takashima; Atsushi Takahashi 001; Yoji Kajitani (ED&TC, 1996)

Module placement on BSG-structure and IC layout applications. - Shigetoshi Nakatake; Kunihiro Fujiyoshi; Hiroshi Murata; Yoji Kajitani (ICCAD, 1996)

VLSI module placement based on rectangle-packing by the sequence-pair. - Hiroshi Murata; Kunihiro Fujiyoshi; Shigetoshi Nakatake; Yoji Kajitani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

A mapping from sequence-pair to rectangular dissection. - Hiroshi Murata; Kunihiro Fujiyoshi; Tomomi Watanabe; Yoji Kajitani (ASP-DAC, 1997)

Performance and reliability driven clock scheduling of sequential logic circuits. - Atsushi Takahashi 001; Yoji Kajitani (ASP-DAC, 1997)

Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. - Atsushi Takahashi 001; Kazunori Inoue; Yoji Kajitani (ICCAD, 1997)

Design of minimum and uniform bipartites for optimum connection blocks of FPGA. - Kunihiro Fujiyoshi; Yoji Kajitani; Hiroshi Niitsu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Air-Pressure-Model-Based Fast Algorithms for General Floorplan. - Tomonori Izumi; Atsushi Takahashi 001; Yoji Kajitani (ASP-DAC, 1998)

Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. - Shigetoshi Nakatake; Masahiro Furuya; Yoji Kajitani (ASP-DAC, 1998)

The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. - Shigetoshi Nakatake; Keishi Sakanushi; Yoji Kajitani; Masahiro Kawakita (ICCAD, 1998)

The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. - Keishi Sakanushi; Shigetoshi Nakatake; Yoji Kajitani (ICCAD, 1998)

Approximating Steiner trees in graphs with restricted weights. - Magnús M. Halldórsson; Shuichi Ueno; Hiroshi Nakao; Yoji Kajitani (Networks, 1998)

Module packing based on the BSG-structure and IC layout applications. - Shigetoshi Nakatake; Kunihiro Fujiyoshi; Hiroshi Murata; Yoji Kajitani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. - Tomoyuki Yoda; Atsushi Takahashi 001; Yoji Kajitani (ASP-DAC, 1999)

Self-reforming routing for stochastic search in VLSI interconnection layout. - Yukiko Kubo; Yasuhiro Takashima; Shigetoshi Nakatake; Yoji Kajitani (ASP-DAC, 2000)

Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. - Yoji Kajitani; Atsushi Takahashi 001; Kengo R. Azegami; Shigetoshi Nakatake (VLSI Design, 2000)

Consistent floorplanning with super hierarchical constraints. - Shigetoshi Nakatake; Yukiko Kubo; Yoji Kajitani (ISPD, 2001)

Chip size estimation based on wiring area. - Yukiko Kubo; Shigetoshi Nakatake; Yoji Kajitani; Masahiro Kawakita (APCCAS (2), 2002)

On the equivalence of the sequence pair for rectangle packing to the dimension of partial orders [floorplanning]. - Hiroshi Miyashita; Yoji Kajitani (APCCAS (2), 2002)

An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. - Changwen Zhuang; Yoji Kajitani; Keishi Sakanushi; Liyan Jin (DATE, 2002)

Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. - Yukiko Kubo; Shigetoshi Nakatake; Yoji Kajitani; Masahiro Kawakita (ASP-DAC/VLSI Design, 2002)

An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm. - Kengo R. Azegami; Masato Inagi; Atsushi Takahashi 001; Yoji Kajitani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Recognition of Floorplan by Parametric BSG for Reuse of Layout Design. - Keishi Sakanushi; Zhonglin Wu; Yoji Kajitani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Consistent floorplanning with hierarchical superconstraints. - Shigetoshi Nakatake; Yukiko Kubo; Yoji Kajitani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost. - Changwen Zhuang; Keishi Sakanushi; Liyan Jin; Yoji Kajitani (ASP-DAC, 2003)

An Incremental Wiring Algorithm for VLSI Layout Design. - Yukiko Kubo; Shigetoshi Nakatake; Yoji Kajitani; Masahiro Kawakita (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Abstraction and optimization of consistent floorplanning with pillar block constraints. - Ning Fu; Shigetoshi Nakatake; Yasuhiro Takashima; Yoji Kajitani (ASP-DAC, 2004)

Multi-level placement with circuit schema based clustering in analog IC layouts. - Takashi Nojima; Xiaoke Zhu; Yasuhiro Takashima; Shigetoshi Nakatake; Yoji Kajitani (ASP-DAC, 2004)

Space-planning: placement of modules with controlled empty area by single-sequence. - Xuliang Zhang; Yoji Kajitani (ASP-DAC, 2004)

Equidistance routing in high-speed VLSI layout design. - Yukiko Kubo; Hiroshi Miyashita; Yoji Kajitani; Kazuyuki Tateishi (ACM Great Lakes Symposium on VLSI, 2004)

A device-level placement with multi-directional convex clustering. - Takashi Nojima; Yasuhiro Takashima; Shigetoshi Nakatake; Yoji Kajitani (ACM Great Lakes Symposium on VLSI, 2004)

Theory of T-junction floorplans in terms of single-sequence. - Xuliang Zhang; Yoji Kajitani (ISCAS (5), 2004)

The oct-touched tile: a new architecture for shape-based routing. - Ning Fu; Shigetoshi Nakatake; Yasuhiro Takashima; Yoji Kajitani (ACM Great Lakes Symposium on VLSI, 2005)

Fixed-outline floorplanning with constraints through instance augmentation. - Rong Liu; Sheqin Dong; Xianlong Hong; Yoji Kajitani (ISCAS (2), 2005)

A new approach based on LFF for optimization of dynamic hardware reconfigurations. - Zhe Zhou; Sheqin Dong; Xianlong Hong; Yuliang Wu; Yoji Kajitani (ISCAS (2), 2005)

A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002; Yoji Kajitani (FPT, 2006)

How does partitioning matter for 3D floorplanning? - Tan Yan; Qing Dong; Yasuhiro Takashima; Yoji Kajitani (ACM Great Lakes Symposium on VLSI, 2006)

Theory of placement by numDAG related with single-sequence, SP, BSG, and O-tree. - Yoji Kajitani (ISCAS, 2006)

Adaptive Porting of Analog IPs with Reusable Conservative Properties. - Takashi Nojima; Nobuto Ono; Shigetoshi Nakatake; Toru Fujimura; Koji Okazaki; Yoji Kajitani (ISVLSI, 2006)

A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002; Yoji Kajitani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Floorplan and Placement. - Yoji Kajitani (Encyclopedia of Algorithms, 2008)

On routing fixed escaped boundary pins for high speed boards. - Tsung-Ying Tsai; Ren-Jie Lee; Ching-Yu Chin; Chung-Yi Kuan; Hung-Ming Chen; Yoji Kajitani (DATE, 2011)

Coding the objects in place and route CAD. - Yoji Kajitani (ISPD, 2013)

Escaped Boundary Pins Routing for High-Speed Boards. - Ching-Yu Chin; Chung-Yi Kuan; Tsung-Ying Tsai; Hung-Ming Chen; Yoji Kajitani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Floorplan and Placement. - Yoji Kajitani (Encyclopedia of Algorithms, 2016)