Multinomial Conjunctoid Statistical Learning Machines. - Yoshiyasu Takefuji; Robert J. Jannarone; Yong B. Cho; Tatung Chen (ISCA, 1988)

Silicon Multinomial Conjunctoid Statistical Learning Modules. - Yoshiyasu Takefuji; Robert J. Jannarone; Tatung Chen; Yong B. Cho (Neural Networks, 1988)

Comments on 'O(n2) algorithms for graph planarization'. - Yoshiyasu Takefuji; Kuo Chun Lee; Yong B. Cho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing. - Baosheng Wang; Yong B. Cho; Sassan Tabatabaei; André Ivanov (Asian Test Symposium, 2003)

Hardware design of CMAC neural network for control applications. - Chan-Mo Kim; Kwang-Ho Choi; Yong B. Cho (IJCNN, 2003)

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices. - Baosheng Wang; Andy Kuo; Touraj Farahmand; André Ivanov; Yong B. Cho; Sassan Tabatabaei (J. Electron. Test., 2005)