A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps. - Yong-Bin Kim; Tom Chen (ASP-DAC, 1997)

Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. - Chris Winstead; Jie Dai; Woo Jin Kim; Scott Little; Yong-Bin Kim; Chris J. Myers; Christian Schlegel (ARVLSI, 2001)

Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems. - Minsu Choi; Nohpill Park; Fabrizio Lombardi; Yong-Bin Kim; Vincenzo Piuri (DFT, 2002)

A Test-Vector Generation Methodology for Crosstalk Noise Faults. - Hamidreza Hashempour; Yong-Bin Kim; Nohpill Park (DFT, 2002)

Design flow of robust routed power distribution for low power ASIC. - Dae Woon Kang; Yong-Bin Kim (ISCAS (1), 2002)

Hardware/Software Co-Reliability of Configurable Digital Systems. - Minsu Choi; Nohpill Park; Yong-Bin Kim; Fabrizio Lombardi (PRDC, 2002)

An accurate DAC modeling technique based on wavelet theory. - James T. Doyle; Young-Jun Lee; Yong-Bin Kim (CICC, 2003)

Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults. - Tao Feng; Nohpill Park; Yong-Bin Kim; Vincenzo Piuri (DFT, 2003)

A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment. - Fengming Zhang; Young-Jun Lee; Thomas Kane; Luca Schiano; Mariam Momenzadeh; Yong-Bin Kim; Fred J. Meyer; Fabrizio Lombardi; Solomon Max; Phil Perkinson (DFT, 2003)

A novel 32-bit scalable multiplier architecture. - Yeshwant Kolla; Yong-Bin Kim; John Carter (ACM Great Lakes Symposium on VLSI, 2003)

A Novel Clocking Strategy for Dynamic Circuits. - Young-Jun Lee; Jong-Jin Lim; Yong-Bin Kim (ISQED, 2003)

Need For Undergraduate And Graduate-Level Education In Testing Of Microelectronic Circuits And Systems. - Minsu Choi; Hardy J. Pottinger; Nohpill Park; Yong-Bin Kim (MSE, 2003)

Optimal Spare Utilization in Repairable and Reliable Memory Cores. - Minsu Choi; Nohpill Park; Fabrizio Lombardi; Yong-Bin Kim; Vincenzo Piuri (MTDT, 2003)

Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. - Minsu Choi; Noh-Jin Park; K. M. George; Byoungjae Jin; Nohpill Park; Yong-Bin Kim; Fabrizio Lombardi (NCA, 2003)

Guest Editors' Introduction: Clockless VLSI Systems. - Soha Hassoun; Yong-Bin Kim; Fabrizio Lombardi (IEEE Des. Test Comput., 2003)

Automating Wave-Pipelined Circuit Design. - Woo Jin Kim; Yong-Bin Kim (IEEE Des. Test Comput., 2003)

Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment. - Young-Jun Lee; Thomas Kane; Jong-Jin Lim; Young Jun Schiano; Yong-Bin Kim; Fred J. Meyer; Fabrizio Lombardi; Solomon Max (IEEE Trans. Instrum. Meas., 2003)

Fault tolerant clockless wave pipeline design. - Tao Feng; Byoungjae Jin; J. Wang; Nohpill Park; Yong-Bin Kim; Fabrizio Lombardi (Conf. Computing Frontiers, 2004)

Scan Test of IP Cores in an ATE Environment. - Luca Schiano; Yong-Bin Kim; Fabrizio Lombardi (DELTA, 2004)

Reliability Modeling and Assurance of Clockless Wave Pipeline. - Tao Feng; Nohpill Park; Yong-Bin Kim; Fabrizio Lombardi; Fred J. Meyer (DFT, 2004)

A fast and precise interconnect capacitive coupling noise model. - Young-Jun Lee; Yong-Bin Kim (ISCAS (2), 2004)

Low power real time electronic neuron VLSI design using subthreshold technique. - Young-Jun Lee; Jihyun Lee; Yong-Bin Kim; Joseph Ayers; Alexander Volkovskii; Allen I. Selverston; Henry D. I. Abarbanel; Mikhail I. Rabinovich (ISCAS (4), 2004)

SRAM word-oriented redundancy methodology using built in self-repair. - Jihyun Lee; Young-Jun Lee; Yong-Bin Kim (SoCC, 2004)

Balanced dual-stage repair for dependable embedded memory cores. - Minsu Choi; Nohpill Park; Vincenzo Piuri; Yong-Bin Kim; Fabrizio Lombardi (J. Syst. Archit., 2004)

A CMOS subbandgap reference circuit with 1-v power supply voltage. - J. Doyle; Young Jun Lee; Yong-Bin Kim; H. Wilsch; Fabrizio Lombardi (IEEE J. Solid State Circuits, 2004)

Fast and accurate DAC modeling techniques based on wavelet theory. - James T. Doyle; Young-Jun Lee; Yong-Bin Kim (Microelectron. J., 2004)

ProSight PTM: an integrated environment for protein identification and characterization by top-down mass spectrometry. - Richard D. LeDuc; Gregory K. Taylor; Yong-Bin Kim; Thomas E. Januszyk; Lee H. Bynum; Joseph V. Sola; John S. Garavelli; Neil L. Kelleher (Nucleic Acids Res., 2004)

On the Modeling and Analysis of Jitter in ATE Using Matlab. - Kyung Ki Kim; Jing Huang 001; Yong-Bin Kim; Fabrizio Lombardi (DFT, 2005)

Data Dependent Jitter (DDJ) Characterization Methodology. - Kyung Ki Kim; Yong-Bin Kim; Fabrizio Lombardi (DFT, 2005)

Quantum-dot cellular automata SPICE macro model. - Rui Tang; Fengming Zhang; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2005)

QCA-based nano circuits design [adder design example]. - Rui Tang; Fengming Zhang; Yong-Bin Kim (ISCAS (3), 2005)

SET-based nano-circuit simulation and design method using HSPICE. - Fengming Zhang; Rui Tang; Yong-Bin Kim (Microelectron. J., 2005)

Environmental-based characterization of SoC-based instrumentation systems for stratified testing. - Noh-Jin Park; K. M. George; Nohpill Park; Minsu Choi; Yong-Bin Kim; Fabrizio Lombardi (IEEE Trans. Instrum. Meas., 2005)

Error Tolerance of DNA Self-Assembly by Monomer Concentration Control. - Byunghyun Jang; Yong-Bin Kim; Fabrizio Lombardi (DFT, 2006)

Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects. - Yadunandana Yellambalase; Minsu Choi; Yong-Bin Kim (DFT, 2006)

Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations. - Fengming Zhang; Warren Necoechea; Peter Reiter; Yong-Bin Kim; Fabrizio Lombardi (DFT, 2006)

PWAM signalling scheme for high speed serial link transceiver design. - Rui Tang; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2006)

A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits. - Rui Tang; Yong-Bin Kim (SoCC, 2006)

ASLIC: A low power CMOS analog circuit design automation. - Jihyun Lee; Yong-Bin Kim (Integr., 2006)

Design metal-dot based QCA circuits using SPICE model. - Rui Tang; Fengming Zhang; Yong-Bin Kim (Microelectron. J., 2006)

Evaluating the Yield of Repairable SRAMs for ATE. - Marco Ottavi; Luca Schiano; Xiaopeng Wang; Yong-Bin Kim; Fred J. Meyer; Fabrizio Lombardi (IEEE Trans. Instrum. Meas., 2006)

Measuring the timing jitter of ATE in the frequency domain. - Luca Schiano; Mariam Momenzadeh; Fengming Zhang; Young-Jun Lee; Thomas Kane; Solomon Max; Philip Perkins; Yong-Bin Kim; Fabrizio Lombardi; Fred J. Meyer (IEEE Trans. Instrum. Meas., 2006)

A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine. - Woon Kang; Yong-Bin Kim; T. Doyle (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture. - Ravi Bonam; Yong-Bin Kim; Minsu Choi (DFT, 2007)

Fault Tolerant Source Routing for Network-on-Chip. - Young Bok Kim; Yong-Bin Kim (DFT, 2007)

Optimal Body Biasing for Minimum Leakage Power in Standby Mode. - Kyung Ki Kim; Yong-Bin Kim (ISCAS, 2007)

A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine Control. - Yong-Bin Kim; Kyung Ki Kim; James T. Doyle (ISCAS, 2007)

Leakage Minimization Technique for Nanoscale CMOS VLSI. - Kyung Ki Kim; Yong-Bin Kim; Minsu Choi; Nohpill Park (IEEE Des. Test Comput., 2007)

Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology. - Kyung Ki Kim; Yong-Bin Kim (IEICE Electron. Express, 2007)

Low power CMOS electronic central pattern generator design for a biomimetic underwater robot. - Young-Jun Lee; Jihyun Lee; Kyung Ki Kim; Yong-Bin Kim; Joseph Ayers (Neurocomputing, 2007)

ProSight PTM 2.0: improved protein identification and characterization for top down mass spectrometry. - Leonid Zamdborg; Richard D. LeDuc; Kevin J. Glowacz; Yong-Bin Kim; Vinayak Viswanathan; Ian T. Spaulding; Bryan P. Early; Eric J. Bluhm; Shannee Babai; Neil L. Kelleher (Nucleic Acids Res., 2007)

Checkpointing of Rectilinear Growth in DNA Self-Assembly. - Stephen Frechette; Yong-Bin Kim; Fabrizio Lombardi (DFT, 2008)

A low leakage 9t sram cell for ultra-low power operation. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (ACM Great Lakes Symposium on VLSI, 2008)

Low power 8T SRAM using 32nm independent gate FinFET technology. - Young Bok Kim; Yong-Bin Kim; Fabrizio Lombardi (SoCC, 2008)

A low power 32 nanometer CMOS digitally controlled oscillator. - Jun Zhao 002; Yong-Bin Kim (SoCC, 2008)

Monomer Control for Error Tolerance in DNA Self-Assembly. - Byunghyun Jang; Yong-Bin Kim; Fabrizio Lombardi (J. Electron. Test., 2008)

Standby power reduction using optimal supply voltage and body-bias voltage. - Kyung Ki Kim; Yong-Bin Kim (IEICE Electron. Express, 2008)

Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels. - Kyung Ki Kim; Jing Huang 001; Yong-Bin Kim; Fabrizio Lombardi (IEEE Trans. Ind. Informatics, 2008)

A Novel Hardened Design of a CMOS Memory Cell at 32nm. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (DFT, 2009)

Errors in DNA Self-Assembly by Synthesized Tile Sets. - Xiaojun Ma; Masoud Hashempour; Yong-Bin Kim; Fabrizio Lombardi (DFT, 2009)

Soft-Error Hardening Designs of Nanoscale CMOS Latches. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (VTS, 2009)

Guest Editorial. - Cristiana Bolchini; Yong-Bin Kim (J. Electron. Test., 2009)

A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates. - Kyung Ki Kim; Yong-Bin Kim; Fabrizio Lombardi (IEEE Trans. Instrum. Meas., 2009)

A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems. - Kyung Ki Kim; Yong-Bin Kim (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Modelling a CNTFET with Undeposited CNT Defects. - Geunho Cho; Fabrizio Lombardi; Yong-Bin Kim (DFT, 2010)

Performance assessment of analog circuits with carbon nanotube FET (CNFET). - Janardhanan S. Ajit; Yong-Bin Kim; Minsu Choi (ACM Great Lakes Symposium on VLSI, 2010)

A low-offset high-speed double-tail dual-rail dynamic latched comparator. - HeungJun Jeon; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2010)

8Gb/s capacitive low power and high speed 4-PWAM transceiver design. - Young Bok Kim; Yong-Bin Kim; Fabrizio Lombardi (ACM Great Lakes Symposium on VLSI, 2010)

Read-out schemes for a CNTFET-based crossbar memory. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (ACM Great Lakes Symposium on VLSI, 2010)

Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems. - Jun Wu; Yong-Bin Kim; Minsu Choi (ACM Great Lakes Symposium on VLSI, 2010)

A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur. - Jun Zhao 002; Yong-Bin Kim (ISQED, 2010)

A 65nm CMOS ultra low power and low noise 131M front-end transimpedance amplifier. - Jiaping Hu; Yong-Bin Kim; Joseph Ayers (SoCC, 2010)

A CMOS low-power low-offset and high-speed fully dynamic latched comparator. - HeungJun Jeon; Yong-Bin Kim (SoCC, 2010)

High speed and low power transceiver design with CNFET and CNT bundle interconnect. - Young Bok Kim; Yong-Bin Kim (SoCC, 2010)

Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (Integr., 2010)

Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems. - HeungJun Jeon; Yong-Bin Kim; Minsu Choi (IEEE Trans. Instrum. Meas., 2010)

A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops. - Jun Zhao 002; Yong-Bin Kim (VLSI Design, 2010)

Database Support for Top-Down Proteomics - Yong-Bin Kim (2010)

Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (ICCD, 2011)

A design approach of a Parametric Measurement Unit on to a 600MHz DCL. - Edward Collins; In-Seok Jung; Yong-Bin Kim; Kyung Ki Kim (ISOCC, 2011)

A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors. - Sheng Lin 006; Yong-Bin Kim; Fabrizio Lombardi (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Hardening a memory cell for low power operation by gate leakage reduction. - Jianping Gong; Yong-Bin Kim; Fabrizio Lombardi; Jie Han 001 (DFT, 2012)

A fully integrated switched-capacitor DC-DC converter with dual output for low power application. - HeungJun Jeon; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2012)

A low stand-by power start-up circuit for SMPS PWM controller. - In-Seok Jung; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2012)

Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit. - Jing Yang; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2012)

A design and integration of Parametric Measurement Unit on to a 600MHz DCL. - Edward Collins; In-Seok Jung; Yong-Bin Kim; Kyung Ki Kim (ISOCC, 2012)

Soft error masking latch for sub-threshold voltage operation. - Yongsuk Choi; Yong-Bin Kim; Fabrizio Lombardi (MWSCAS, 2012)

A novel 4-to-3 step-down on-chip SC DC-DC converter with reduced bottom-plate loss. - HeungJun Jeon; Yong-Bin Kim; Kyung Ki Kim (MWSCAS, 2012)

A novel sort error hardened 10T SRAM cells for low voltage operation. - In-Seok Jung; Yong-Bin Kim; Fabrizio Lombardi (MWSCAS, 2012)

All-digital phased-locked loop with local passive interpolation time-to-digital converter based on a tristate inverter. - Moon Seok Kim; Yong-Bin Kim; Kyung Ki Kim (MWSCAS, 2012)

Design and evaluation of Side Channel Attack resistant asynchronous AES Round Function. - Siva Pavan Kumar Kotipalli; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (MWSCAS, 2012)

On-chip HBD sensor for nanoscale CMOS technology. - Ho Joon Lee; Yong-Bin Kim; Kyung Ki Kim (MWSCAS, 2012)

Low power, high PVT variation tolerant central pattern generator design for a bio-hybrid micro robot. - Jing Lu; Jing Yang; Yong-Bin Kim; Joseph Ayers (MWSCAS, 2012)

A high speed low power modulo 2n+1 multiplier design using carbon-nanotube technology. - He Qi; Yong-Bin Kim; Minsu Choi (MWSCAS, 2012)

Configurable logic block (CLB) design for Asynchronous Nanowire Crossbar system. - Jun Wu; Yong-Bin Kim; Minsu Choi (MWSCAS, 2012)

Post-configuration repair strategy for asynchronous nanowire crossbar system. - Jun Wu; Yong-Bin Kim; Minsu Choi (MWSCAS, 2012)

Design and analysis of the quadfferential amplifier. - Tina Marie Rookmaaker; Moon Seok Kim; Yong-Bin Kim (Microelectron. J., 2012)

A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter. - In-Seok Jung; Yong-Bin Kim (IEEE Trans. Ind. Electron., 2012)

A switched-capacitor DC-DC converter using delta-sigma digital pulse frequency modulation control method. - Yongsuk Choi; HeungJun Jeon; Yong-Bin Kim (MWSCAS, 2013)

A 10-bit 64MS/s SAR ADC using variable clock period method. - In-Seok Jung; Marvin Onabajo; Yong-Bin Kim (MWSCAS, 2013)

Low power Null Convention Logic circuit design based on DCVSL. - Ho Joon Lee; Yong-Bin Kim (MWSCAS, 2013)

A high performance modulo 2n+1 squarer design based on carbon nanotube technology. - Weifu Li; Yong-Bin Kim (MWSCAS, 2013)

A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA. - Yongsuk Choi; Chun-hsiang Chang; In-Seok Jung; Marvin Onabajo; Yong-Bin Kim (DFT, 2014)

A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch. - In-Seok Jung; Yong-Bin Kim (DFT, 2014)

A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers. - Yongsuk Choi; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2014)

An area efficient low power high speed S-Box implementation using power-gated PLA. - Ho Joon Lee; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2014)

A low power high resolution digital PWM with process and temperature calibrations for digital controlled DC-DC converters. - Jing Lu; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2014)

A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers. - Yongsuk Choi; Chun-hsiang Chang; Hari Chauhan; In-Seok Jung; Marvin Onabajo; Yong-Bin Kim (MWSCAS, 2014)

A novel self-calibration scheme for 12-bit 50MS/s SAR ADC. - In-Seok Jung; Yong-Bin Kim (MWSCAS, 2014)

Full custom implementation of a S-Box circuit architecture using power gated PLA structure. - Ho Joon Lee; Yong-Bin Kim; Kyung Ki Kim (MWSCAS, 2014)

Calibration technique tracking temperature for current-steering digital-to-analog converters. - Haiyang Zhu; Wenhua Yang 002; Nathan Egan; Yong-Bin Kim (MWSCAS, 2014)

Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance. - Siva Kotipalli; Yong-Bin Kim; Minsu Choi (J. Electr. Comput. Eng., 2014)

Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches. - Hari Chauhan; Yongsuk Choi; Marvin Onabajo; In-Seok Jung; Yong-Bin Kim (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer. - Yongsuk Choi; Yong-Bin Kim (MWSCAS, 2015)

A process tolerant semi-self impedance calibration method for LPDDR4 memory controller. - Ho Joon Lee; Yong-Bin Kim (MWSCAS, 2015)

Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier. - Haiyang Zhu; Ron Kapusta; Yong-Bin Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC. - Yongsuk Choi; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2016)

Integrated circuits design using carbon nanotube field effect transistor. - Yong-Bin Kim (ISOCC, 2016)

Hybrid GDI-NCL for area/power reduction. - Prashanthi Metku; Ramu Seva; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (ISOCC, 2016)

Parallel decoding for multi-stage BCH decoder. - Prashanthi Metku; Ramu Seva; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (ISOCC, 2016)

Approximate stochastic computing (ASC) for image processing applications. - Ramu Seva; Prashanthi Metku; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (ISOCC, 2016)

A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration. - Yongsuk Choi; Yong-Bin Kim; In-Seok Jung (NATW, 2016)

An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction. - Chen Zhang; Gyunam Jeon; Yongsuk Choi; Yong-Bin Kim; Kyung Ki Kim (NATW, 2016)

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories. - Wei Wei 034; Kazuteru Namba; Yong-Bin Kim; Fabrizio Lombardi (IEEE Trans. Computers, 2016)

Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data Rate. - Gyunam Jeon; Yong-Bin Kim (ACM Great Lakes Symposium on VLSI, 2017)

A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction. - Gyunam Jeon; Yong-Bin Kim (ISCAS, 2017)

Time-domain temperature sensor based on interlaced hysteresis delay cells. - Yun Seok Hong; Yong-Bin Kim; Kyung Ki Kim (ISOCC, 2017)

A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap. - Gyunam Jeon; Yong-Bin Kim (ISOCC, 2017)

Low-power null convention logic design based on modified gate diffusion input technique. - Prashanthi Metku; Ramu Seva; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (ISOCC, 2017)

Variable bit truncation technique for approximate stochastic computing (ASC). - Ramu Seva; Prashanthi Metku; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (ISOCC, 2017)

Global clock distribution on standing wave with CMOS active inductor loading. - Jing Yang; Yong-Bin Kim (MWSCAS, 2017)

Fully Integrated on-Chip Switched DC-DC Converter for Battery-Powered Mixed-Signal SoCs. - HeungJun Jeon; Kyung Ki Kim; Yong-Bin Kim (Symmetry, 2017)

A Two-Parameter Calibration Technique Tracking Temperature Variations for Current Source Mismatch. - Haiyang Zhu; Wenhua Yang 002; Gil Engel; Yong-Bin Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique. - Prashanthi Metku; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (ISOCC, 2018)

Generalized Adaptive Variable Bit Truncation Method for Approximate Stochastic Computing. - Keerthana Pamidimukkala; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (ISOCC, 2018)

Low Power Digital Temperature Sensor Using Modified Inverter Interlaced Cascaded Delay Cell. - Yun Seok Hong; Yong-Bin Kim (MWSCAS, 2018)

Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor. - Gyunam Jeon; Yong-Bin Kim (MWSCAS, 2018)

Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme. - Yongsuk Choi; Gyunam Jeon; Yong-Bin Kim (Integr., 2018)

Evaluations of Electronic Neuron Model for Low Power VLSI Implementation. - Yixuan He; Kyung Ki Kim; Yong-Bin Kim (ISOCC, 2019)

Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation. - Gyunam Jeon; Kyung Ki Kim; Yong-Bin Kim (ISOCC, 2019)

Optimization of Null Convenction Logic Using Gate Diffusion Input. - Prashanthi Metku; Minsu Choi; Kyung Ki Kim; Yong-Bin Kim (ISOCC, 2019)

Area Efficient Multi-Threshold Null Convenction Logic. - Prashanthi Metku; Minsu Choi; Kyung Ki Kim; Yong-Bin Kim (ISOCC, 2019)

10 GHz Standing Wave Oscillator Based Clock Distribution Network Considering Distributed Capacitance. - Gyunam Jeon; Yong-Bin Kim (MWSCAS, 2019)

Peak Current Control Boost Converter with Time-Multiplex. - Elizabeth Amyouny; Yixuan He; Kyung Ki Kim; Yong-Bin Kim (ISOCC, 2020)

An Ultra-Low-Power Tunable Bump Circuit using Source-Degenerated Differential Transconductor. - Yixuan He; Minsu Choi; Kyung Ki Kim; Yong-Bin Kim (ISOCC, 2020)

Gate Diffusion Input Multi-Threshold Null Convention Logic Circuit Design Approach. - Prashanthi Metku; Minsu Choi; Kyung Ki Kim; Yong-Bin Kim (ISOCC, 2020)

A Tunable High-Gain Low-Noise Transimpedance Amplifier for Biosensing. - Yixuan He; Minsu Choi; Yong-Bin Kim (MWSCAS, 2020)

A Time-Domain Computing-In-Memory Micro using Ring Oscillator. - Yixuan He; Minsu Choi; Kyung Ki Kim; Yong-Bin Kim (ISOCC, 2021)

Stochastic Edge Detection for Fine-Grained Progressive Precision. - Youngwook Lee; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (ISOCC, 2021)

FPGA-based Scalable Road Image Stochastic Denosing Approach. - Cheolhyeong Park; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (ISOCC, 2021)

A Stray-Insensitive Low-Power Capacitive Sensor Interface with Time-Compensation Technique. - Yixuan He; Yong-Bin Kim (MWSCAS, 2021)

A Time-Domain Parallel Counter for Deep Learning Macro. - Yixuan He; Minsu Choi; Kyung Ki Kim; Yong-Bin Kim (ISOCC, 2022)

Time-Efficient Approximate Stochastic Computing for Medical Imaging Applications. - Keerthana Pamidimukkala; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (ISOCC, 2022)

Low-Power Counters using Pathfinding Technique. - Yixuan He; Minsu Choi; Kyung-Ki Kim; Yong-Bin Kim (ISOCC, 2023)

Modeling Truncation-Based Approximation Error in Stochastic Computing Circuits. - Keerthana Pamidimukkala; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (ISOCC, 2023)

A Novel Area Efficient Approximate Stochastic Computing Approach for Edge Devices. - Keerthana Pamidimukkala; Kyung Ki Kim; Yong-Bin Kim; Minsu Choi (ISOCC, 2024)