Sequential test generators: past, present and future. - Yong Chang Kim; Kewal K. Saluja (Integr., 1998)

A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. - Yong Chang Kim; Kewal K. Saluja; Vishwani D. Agrawal (Great Lakes Symposium on VLSI, 1999)

Combinational test generation for various classes of acyclic sequential circuits. - Yong Chang Kim; Vishwani D. Agrawal; Kewal K. Saluja (ITC, 2001)

Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. - Yong Chang Kim; Kewal K. Saluja; Vishwani D. Agrawal (VLSI Design, 2001)

Multiple Faults: Modeling, Simulation and Test. - Yong Chang Kim; Vishwani D. Agrawal; Kewal K. Saluja (ASP-DAC/VLSI Design, 2002)

Exclusive Test and its Applications to Fault Diagnosis. - Vishwani D. Agrawal; Dong Hyun Baik; Yong Chang Kim; Kewal K. Saluja (VLSI Design, 2003)

Combinational automatic test pattern generation for acyclic sequential circuits. - Yong Chang Kim; Vishwani D. Agrawal; Kewal K. Saluja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)