Source-follower-based bi-quad cell for continuous-time zero-pole type filters. - Yong Chen 005; Pui-In Mak; Yumei Zhou (ISCAS, 2010)

A Single-Branch Third-Order Pole-Zero Low-Pass Filter With 0.014-mm2 Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth-Power Scalability. - Yong Chen 005; Pui-In Mak; Stefano D'Amico; Li Zhang 046; He Qian; Yan Wang 023 (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Fifth-Order 20-MHz Transistorized-LC-Ladder LPF With 58.2-dB SFDR, 68-µW/Pole/MHz Efficiency, and 0.13-mm2 Die Size in 90-nm CMOS. - Yong Chen 005; Pui-In Mak; Li Zhang 046; He Qian; Yan Wang 023 (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links. - Yong Chen 005; Pui-In Mak; Yan Wang 023 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin. - Yong Chen 005; Pui-In Mak; Chirn Chye Boon; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications. - Lingshan Kong; Yong Chen 005; Chirn Chye Boon; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS. - Arya Balachandran; Yong Chen 005; Chirn Chye Boon (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS. - Arya Balachandran; Yong Chen 005; Chirn Chye Boon (APCCAS, 2019)

Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. - Lingshan Kong; Yong Chen 005; Haohong Yu; Quan Pan 002; Chirn Chye Boon; Pui-In Mak; Rui Paulo Martins (APCCAS, 2019)

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (APCCAS, 2019)

A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS. - Zunsong Yang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2019)

A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6dBc/Hz FoM and 130kHz 1/f3 PN Corner. - Hao Guo; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (ISSCC, 2019)

A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur. - Zunsong Yang; Yong Chen 005; Shiheng Yang; Pui-In Mak; Rui Paulo Martins (ISSCC, 2019)

A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis. - Yong Chen 005; Pui-In Mak; Zunsong Yang; Chirn Chye Boon; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 0.044-mm2 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB. - Haohong Yu; Yong Chen 005; Chirn Chye Boon; Chenyang Li 008; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter. - Xinyi Ge; Yong Chen 005; Xiaoteng Zhao; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (CICC, 2020)

A 0.024-mm2 45.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz. - Yong Chen 005; Pui-In Mak; Chirn Chye Boon; Rui Paulo Martins (MWSCAS, 2020)

A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector. - Zunsong Yang; Yong Chen 005; Shiheng Yang; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2020)

A 3.3-mW 25.2-to-29.4-GHz Current-Reuse VCO Using a Single-Turn Multi-Tap Inductor and Differential-Only Switched-Capacitor Arrays With a 187.6-dBc/Hz FOM. - Yunbo Huang; Yong Chen 005; Hao Guo; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects. - Donglai Lu; Jian He; Weizhong Li; Sikai Chen; Jian Liu 021; Nanjian Wu; Ningmei Yu; Liyuan Liu; Yong Chen 005; Xi Xiao; Nan Qi (APCCAS, 2021)

A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process. - Jincheng Zhang; Tianxiang Wu; Yong Chen 005; Junyan Ren; Shunli Ma (A-SSCC, 2021)

A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio. - Dong Wei 008; Tianxiang Wu; Shunli Ma; Yong Chen 005; Junyan Ren (ESSCIRC, 2021)

A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS. - Chen Cai; Xuqiang Zheng; Yong Chen 005; Danyu Wu; Jian Luan 002; Lei Zhou 014; Jin Wu; Xinyu Liu 004 (ESSCIRC, 2021)

A 4×25Gb/s De-Serializer with Baud-Rate Sampling CDR and Standing-Wave Clock Distribution for NIC Optical Interconnects. - Mingyang You; Minjia Chen; Yihong Li; Guike Li; Jian Liu 021; Yong Chen 005; Yingtao Li; Nan Qi (ICTA, 2021)

A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects. - Ming Zhong; Qingwen Wang; Yong Chen 005; Jian Liu 021; Liyuan Liu; Xinghua Wang; Xiaoming Xiong; Nan Qi (ICTA, 2021)

A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation, Achieving -151-dBc/Hz Phase Noise at 10-MHz Offset. - Yunbo Huang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (ISCAS, 2021)

A 5.0-to-6.36GHz Wideband-Harmonic-Shaping VCO Achieving 196.9dBc/Hz Peak FoM and 90-to-180kHz 1/f3 PN Corner Without Harmonic Tuning. - Hao Guo; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (ISSCC, 2021)

Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. - Lingshan Kong; Yong Chen 005; Haohong Yu; Chirn Chye Boon; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2021)

A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS. - Manxin Li; Yuting Yao; Biao Hu; Jipeng Wei; Yong Chen 005; Shunli Ma; Fan Ye 001; Junyan Ren (IEEE Access, 2021)

A 120-150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm Psat for Sub-THz Imaging System. - Jincheng Zhang; Tianxiang Wu; Lihe Nie; Shunli Ma; Yong Chen 005; Junyan Ren (IEEE Access, 2021)

Bird's-eye view of analog and mixed-signal chips for the 21st century. - Rui Paulo Martins; Pui-In Mak; Chi-Hang Chan; Jun Yin 001; Yan Zhu 001; Yong Chen 005; Yan Lu 002; Man-Kay Law; Sai-Weng Sin (Int. J. Circuit Theory Appl., 2021)

An accelerated architecture of change-point detection for FMCW radar mutual interference based on FPGA. - Siyuan Yang 003; Songyi Li; Jiayan Wu; Yong Chen 005; Zhenyu Liu (Int. J. Circuit Theory Appl., 2021)

A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS. - Zunsong Yang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 3.36-GHz Locking-Tuned Type-I Sampling PLL With -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques. - Yunbo Huang; Yong Chen 005; Hailong Jiao; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-Distorter (DAAPD) Reconfigurable Linearization Technique. - Selvakumar Mariappan; Jagadheswaran Rajendran; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS. - Yihong Li; Sikai Chen; Yunqi Yang; Qianli Ma; Ming Zhong; Ziyi Lin; Leliang Li; Guike Li; Zhao Zhang 004; Liyuan Liu; Jian Liu 021; Nanjian Wu; et al. (APCCAS, 2022)

A 0.004-mm2 O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL. - Yixi Li; Xinyu Shen; Zhaoyu Zhang; Guike Li; Tao Yin; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yong Chen 005; Zhao Zhang 004 (APCCAS, 2022)

A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15µ m GaAs pHEMT Process. - Wenyang Liu; Tianxiang Wu; Tianyang Yan; Fan Yang 001; Yong Chen 005; Shunli Ma (APCCAS, 2022)

A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop. - Zhaoyu Zhang; Xinyu Shen; Yixi Li; Guike Li; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yong Chen 005; Zhao Zhang 004 (APCCAS, 2022)

A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE. - Zhiyang Zhang; Xi Wang; Yong Chen 005; Junyan Ren; Shunli Ma (APCCAS, 2022)

A Battery-Less Crystal-Less 49.8µW Neural-Recording Chip Featuring Two-Tone RF Power Harvesting. - Ziyi Chang; Changgui Yang; Yunshan Zhang; Zhuhao Li; Tianyu Zheng; Yuxuan Luo; Shaomin Zhang; Kedi Xu 001; Gang Pan 001; Bo Zhao 003; Yong Chen 005 (CICC, 2022)

A Power-Harvesting CGM Chiplet Featuring Silicon-Based Enzymatic Glucose Sensor. - Ting-Hsun Wang; Zhuhao Li; Bo Liang; Yu Cai 015; Zhiyu Wang; Changgui Yang; Yuxuan Luo; Jiabao Sun; Xuesong Ye; Yong Chen 005; Bo Zhao 003 (EMBC, 2022)

A 0.01mm2, 0.4V-VDD, 4.5nW-Power DC-Coupled Digital Acquisition Front-End Based on Time-Multiplexed Digital Differential Amplification. - Paolo Crovetti; Roberto Rubino; Pedro Toledo; Francesco Musolino; Hamilton Klimach; Yong Chen 005; Anna Richelli (ESSCIRC, 2022)

A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link. - Xiongshi Luo; Xuewei You; Jiahan Fu; Zhenghao Li; Liping Zhong; Taiyang Fan; Zhang Qiu; Wenbo Xiao; Yong Chen 005; Quan Pan 002 (ESSCIRC, 2022)

A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme. - Lin Wang 115; Yong Chen 005; Chaowei Yang; Xiaoteng Zhao; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (ICECS 2022, 2022)

A Flexible-Window Filtering Technique for Interference Suppression in SpO2 Monitoring. - Xin Hu; Yuxuan Luo; Yong Chen 005; Bo Zhao 003 (ISCAS, 2022)

A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector. - Xinyi Ge; Yong Chen 005; Lin Wang 115; Nan Qi; Pui-In Mak; Rui Paulo Martins (NorCAS, 2022)

Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review. - Tan Yee Chyan; Harikrishnan Ramiah; Sharifah Wan Muhamad Hatta; Nai Shyan Lai; Chee-Cheow Lim; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2022)

Low Voltage Switched-Capacitive-Based Reconfigurable Charge Pumps for Energy Harvesting Systems: An Overview. - Tian Siang Ho; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Yong Chen 005; Chee-Cheow Lim; Nai Shyan Lai; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2022)

A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology. - Tianxiang Wu; Xi Wang; Yong Chen 005; Junyan Ren; Shunli Ma (Int. J. Circuit Theory Appl., 2022)

A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs. - Zhiyang Zhang; Lihe Nie; Jincheng Zhang; Tianxiang Wu; Yong Chen 005; Junyan Ren; Shunli Ma (Int. J. Circuit Theory Appl., 2022)

A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR. - Qiwen Liao; Yuguang Zhang; Siyuan Ma; Lei Wang 187; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yong Chen 005; Xi Xiao; et al. (IEEE J. Solid State Circuits, 2022)

A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration. - Qihui Zhang; Ning Ning 002; Zhong Zhang 002; Jing Li 022; Kejun Wu; Yong Chen 005; Qi Yu 002 (IEEE J. Solid State Circuits, 2022)

A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Lin Wang 115; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A Fully-Integrated Ambient RF Energy Harvesting System with 423-μW Output Power. - Kishore Kumar Pakkirisami Churchill; Harikrishnan Ramiah; Gabriel Chong; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (Sensors, 2022)

A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection. - Qirui Ren; Chengying Chen; Danian Dong; Xiaoxin Xu; Yong Chen 005; Feng Zhang 014 (Sensors, 2022)

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components. - Mengdi Zhang; Ye Zhao; Yong Chen 005; Paolo Crovetti; Yanji Wang; Xinshun Ning; Shushan Qiao (Sensors, 2022)

Correction: Zhang et al. A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components. Sensors 2022, 22, 5852. - Mengdi Zhang; Ye Zhao; Yong Chen 005; Paolo Crovetti; Yanji Wang; Xinshun Ning; Shushan Qiao (Sensors, 2022)

A Crystal-Less Clock Generation Technique for Battery-Free Wireless Systems. - Ziyi Chang; Yunshan Zhang; Changgui Yang; Yuxuan Luo; Sijun Du; Yong Chen 005; Bo Zhao 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

APCCAS 2021 Guest Editorial. - Yong Chen 005; Harikrishnan Ramiah (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Millimeter-Wave CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RLCM Tank. - Hao Guo; Yong Chen 005; Chaowei Yang; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects. - Jian He; Donglai Lu; Haiyun Xue; Sikai Chen; Han Liu; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Liyuan Liu; Nanjian Wu; Ningmei Yu; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS. - Jian He; Yuguang Zhang; Han Liu; Qiwen Liao; Zhao Zhang 004; Miaofeng Li; Fan Jiang; Jingbo Shi; Jian Liu 021; Nanjian Wu; Yong Chen 005; Patrick Yin Chiang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

High-Performance Harmonic-Rich Single-Core VCO With Multi-LC Tank: A Tutorial. - Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Square-Wave Stimulated DNA Analyzer Chip Featuring 120μW Power Consumption and Simultaneous Dual-Frequency Detection. - Xiangdong Feng; Yunshan Zhang; Yangfan Xuan; Zhuhao Li; Changgui Yang; Xin Xie; Yuxuan Luo; Xiangwei Zhao; Yong Chen 005; Bo Zhao 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.1-V VIN Subthreshold 3-Stage Dual-Branch Charge Pump With 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias. - Jack Kee Yong; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Gabriel Chong; Saad Mekhilef; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 6.5-mm2 10.5-to-15.5-GHz Differential GaN PA With Coupled-Line-Based Matching Networks Achieving 10-W Peak Psat and 42% PAE. - Jincheng Zhang; Lihe Nie; Yong Chen 005; Junyan Ren; Shunli Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting. - Alexander Choo Chia Chun; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Yong Chen 005; Saad Mekhilef; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A -20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN. - Wen Xun Lian; Harikrishnan Ramiah; Gabriel Chong; Kishore Kumar Pakkirisami Churchill; Nai Shyan Lai; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM. - Zunsong Yang; Yong Chen 005; Jia Yuan; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. - Yixi Li; Zhao Zhang 004; Yong Chen 005; Xinyu Shen; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (A-SSCC, 2023)

A 72-Channel Resistive-and-Capacitive Sensor Interface Achieving 0.74 μ W/ Channel and 0.038 mm2/ Channel by Noise-Orthogonalizing and Pad-Sharing Techniques. - Xiangdong Feng; Yuxuan Luo; Tianyi Cai; Yangfan Xuan; Yunshan Zhang; Yili Shen; Changgui Yang; Qijing Xiao; Yong Chen 005; Bo Zhao 003 (CICC, 2023)

A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM. - Xinyu Shen; Zhao Zhang 004; Guike Li; Yong Chen 005; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (ESSCIRC, 2023)

A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE. - Zhaoyu Zhang; Zhao Zhang 004; Yong Chen 005; Guoqing Wang; Xinyu Shen; Nan Qi; Guike Li; Shuangming Yu; Jian Liu 021; Nanjian Wu; Liyuan Liu (ESSCIRC, 2023)

A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2nd-Harmonic Output. - Yunbo Huang; Yong Chen 005; Chaowei Yang; Pui-In Mak; Rui Paulo Martins (ISCAS, 2023)

An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz $ text{FoM}_{ mathrm{T}}$. - Hao Guo; Yong Chen 005; Yunbo Huang; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur. - Zhao Zhang 004; Xinyu Shen; Zhaoyu Zhang; Guike Li; Nan Qi; Jian Liu 021; Yong Chen 005; Nanjian Wu; Liyuan Liu (ISSCC, 2023)

A 880 nW, 100 kS/s, 13 bit Differential Relaxation-DAC in 180 nm. - Roberto Rubino; Francesco Musolino; Yong Chen 005; Anna Richelli; Paolo Crovetti (PRIME, 2023)

A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS. - Zhao Zhang 004; Zhaoyu Zhang; Yong Chen 005; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (VLSI Technology and Circuits, 2023)

Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low Voltage Mobile Applications: A Review. - Li Fang Lai; Harikrishnan Ramiah; Tan Yee Chyan; Nai Shyan Lai; Chee-Cheow Lim; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

High-Performance Multiband Ambient RF Energy Harvesting Front-End System for Sustainable IoT Applications - A Review. - Yi Chen Lee; Harikrishnan Ramiah; Alexander Choo Chia Chun; Kishore Kumar Pakkirisami Churchill; Nai Shyan Lai; Chee-Cheow Lim; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

A Fully-Integrated CMOS Dual-Band RF Energy Harvesting Front-End Employing Adaptive Frequency Selection. - Wen Xun Lian; Harikrishnan Ramiah; Gabriel Chong; Kishore Kumar Pakkirisami Churchill; Nai Shyan Lai; Saad Mekhilef; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application. - Jack Kee Yong; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Gabriel Chong; Saad Mekhilef; Nai Shyan Lai; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, -258.7-dB FOM, and -75.17-dBc Reference Spur. - Yunbo Huang; Yong Chen 005; Bo Zhao 003; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF. - Qirui Ren; Qiang Huo; Zhisheng Chen; Qi Gao; Yiming Wang; Yiming Yang; Hao Wu 084; Xiangqu Fu; Xiaoxin Xu; Qing Luo; Jianfeng Gao 005; Chengying Chen; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique. - Yujia Wang; Jincheng Zhang; Yong Chen 005; Junyan Ren; Shunli Ma (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor. - Xi Wang; Dong Wei 008; Zhiyang Zhang; Tianxiang Wu; Xu Chen; Yong Chen 005; Junyan Ren; Shunli Ma (Int. J. Circuit Theory Appl., 2023)

A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMS Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur. - Yunbo Huang; Yong Chen 005; Bo Zhao 003; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Universal Stability Criterion for Type-I Sampling Phase-Locked Loops. - Yunbo Huang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation. - Lin Wang 115; Yong Chen 005; Chaowei Yang; Xionghui Zhou; Mei Han; Paolo Stefano Crovetti; Pui-In Mak; Rui Paulo Martins (Int. J. Circuit Theory Appl., 2023)

A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique. - Lin Wang 115; Yong Chen 005; Chaowei Yang; Xiaoteng Zhao; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting. - Alexander Choo Chia Chun; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Yong Chen 005; Saad Mekhilef; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network. - Yuchen Wei; Shiheng Yang; Yueduo Liu; Rongxin Bao; Zihao Zhu; Jiahui Lin; Zehao Zhang; Yong Chen 005; Jun Yin 001; Pui-In Mak; Qiang Li 021 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A High-PCE Range-Extension CMOS Rectifier Employing Advanced Topology Amalgamation Technique for Ambient RF Energy Harvesting. - Alexander Choo Chia Chun; Yi Chen Lee; Harikrishnan Ramiah; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application. - Kishore Kumar Pakkirisami Churchill; Harikrishnan Ramiah; Alexander Choo Chia Chun; Gabriel Chong; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS. - Chenghao Zhang; Jiangbo Wei; Yong Chen 005; Maliang Liu; Yintang Yang (IEEE J. Solid State Circuits, 2023)

A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O. - Sikai Chen; Mingyang You; Yunqi Yang; Ye Jin; Ziyi Lin; Yihong Li; Leliang Li; Guike Li; Yujun Xie; Zhao Zhang 004; Binhao Wang; Ningfeng Tang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 28-nm 368-fJ/Cycle, 0.43%/V Supply-Sensitivity, FLL-Based RC Oscillator Featuring Positive-TC-Only Resistors and ΔΣM-Based Trimming. - Yunbo Huang; Yong Chen 005; Kaiyuan Yang 001; Paolo Crovetti; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer. - Xiangqu Fu; Qirui Ren; Hao Wu 084; Feibin Xiang; Qing Luo; Jinshan Yue; Yong Chen 005; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Fully Integrated CMOS Tri-Band Ambient RF Energy Harvesting System for IoT Devices. - Jack Kee Yong; Wen Xun Lian; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Gabriel Chong; Nai Shyan Lai; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 0.0006-mm2 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS. - Zhicheng Dong; Xiaoteng Zhao; Zekai Yang; Xianting Su; Haolin Han; Feng Bu; Rong Zhou; Depeng Sun; Yong Chen 005; Shubin Liu; Ruixue Ding; Zhangming Zhu (A-SSCC, 2024)

A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation. - Xinyu Shen; Zhao Zhang 004; Yong Chen 005; Yixi Li; Yidan Zhang; Guike Li; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (CICC, 2024)

7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur. - Yunbo Huang; Yong Chen 005; Zunsong Yang; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur. - Tianle Chen; Hongyu Ren; Zunsong Yang; Yunbo Huang; Xianghe Meng; Weiwei Yan; Weidong Zhang; Xuqiang Zheng; Xuan Guo; Tetsuya Iizuka; Pui-In Mak; Yong Chen 005; et al. (VLSI Technology and Circuits, 2024)

A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity. - Hao Wu 084; Yong Chen 005; Yiyang Yuan; Jinshan Yue; Xiangqu Fu; Qirui Ren; Qing Luo; Pui-In Mak; Xinghua Wang; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Extended Power Dynamic Range and Enhanced Power Conversion Efficiency of a Switched-Capacitor DC-DC Converter: A Tutorial. - Tian Siang Ho; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70-400-kHz 1/f³ PN Corner Over 4.9-7.3-GHz TR. - Shan Lu; Danyu Wu; Xuan Guo; Hanbo Jia; Yong Chen 005; Xinyu Liu 004 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 0.012-mm2 0.244-pJ/bit successive approximation register analog-to-digital converter-based true random number generator for Internet of Things applications in a 65-nm complementary metal-oxide-semiconductor. - Kai Cheng; Yong Chen 005; Paolo Stefano Crovetti; Rui Paulo Martins; Pui-In Mak (Int. J. Circuit Theory Appl., 2024)

A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2nd Harmonic Extraction Achieving 45.8fsrms Jitter and -254.3dB FoM. - Yunbo Huang; Zunsong Yang; Hongyu Ren; Rui Paulo Martins; Yan Lu 002; Nan Sun 001; Nan Qi; Yong Chen 005 (CICC, 2025)

A 0.16mm2450MHz-BW 72dB-SNDR Continuous-time Pipeline ADC with APF+HPF and APF+FIR Hybrid Delay Alignment Techniques. - Heyang Zhao; Yuxuan He; Yunsong Tao; Zhishuai Zhang; Yong Chen 005; Yi Zhong; Lu Jie 001; Nan Sun 001 (CICC, 2025)

Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS. - Roberto Rubino; Francesco Musolino; Pedro Toledo; Yong Chen 005; Anna Richelli; Paolo Stefano Crovetti (IEEE Access, 2025)

Evolution of and Perspectives on Differential-Pair-Based CMOS Variable Gain Amplifiers With Linear-in-Decibel Gain Control: A Tutorial. - Siqi Wang; Zhenghao Lu; Zhong Tang; Xiaopeng Yu 002; Hanming Wu; Kiat Seng Yeo; Yong Chen 005 (Int. J. Circuit Theory Appl., 2025)

A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity. - Hao Wu 084; Yong Chen 005; Yiyang Yuan; Jinshan Yue; Xinghua Wang; Xiaoran Li; Feng Zhang 014 (IEEE J. Solid State Circuits, 2025)

A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving. - Sihao Chen; Chengyu Huang 001; Limeng Sun; Yang Liu; Wenjun Tang; Jiaxuan Fan; Nan Sun 001; Yong Chen 005; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal-oxide-semiconductor. - Chaowei Yang; Yong Chen 005; Kai Cheng; Paolo Stefano Crovetti; Rui Paulo Martins; Pui-In Mak (Int. J. Circuit Theory Appl., 2025)

A Harmonic-Suppressed GaN Power Amplifier Using Artificial Coupled Resonator. - Letian Guo; Jincheng Zhang; Lihe Nie; Jian Wang; Yong Chen 005; Junyan Ren; Shunli Ma (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS. - Shan Lu; Danyu Wu; Xuan Guo; Hanbo Jia; Yong Chen 005; Xinyu Liu 004 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Capacitorless Flipped-Voltage-Follower-Based Low-Dropout Regulator Incorporating Adaptive-Compensation Buffer. - Tan Yee Chyan; Harikrishnan Ramiah; Sharifah Wan Muhamad Hatta; Chee-Cheow Lim; Rui Paulo Martins; Pui-In Mak; Yong Chen 005 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Switch-as-Resistor Self-Adaptive Gate-Biasing Technique for Optimized Forward and Reverse Conduction in a CMOS Rectifier. - Yi Chen Lee; Harikrishnan Ramiah; Tian Siang Ho; Fu Qi Chua; Wen Xun Lian; Kishore Kumar Pakkirisami Churchill; Yong Chen 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)